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llvm/test/CodeGen
Craig Topper 8513fb6993 [X86] Add a DAG combine to shrink vXi64 gather/scatter indices that are constant with sufficient sign bits to fit in vXi32
The gather/scatter instructions can implicitly sign extend the indices. If we're operating on 32-bit data, an v16i64 index can force a v16i32 gather to be split in two since the index needs 2 registers. If we can shrink the index to the i32 we can avoid the split. It should always be safe to shrink the index regardless of the number of elements. We have gather/scatter instructions that can use v2i32 index stored in a v4i32 register with v2i64 data size.

I've limited this to before legalize types to avoid creating a v2i32 after type legalization. We could check for it, but we'd also need testing. I'm also only handling build_vectors with no bitcasts to be sure the truncate will constant fold.

Differential Revision: https://reviews.llvm.org/D68247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373408 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-01 23:18:31 +00:00
..
2019-10-01 18:53:54 +00:00
2019-07-04 06:12:47 +00:00
2019-07-30 19:52:01 +00:00