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212514f179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210968 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
3.6 KiB
C++
114 lines
3.6 KiB
C++
//===----------------------- AMDGPUFrameLowering.cpp ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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// Interface to describe a layout of a stack frame on a AMDIL target machine
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPURegisterInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Instructions.h"
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using namespace llvm;
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AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
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int LAO, unsigned TransAl)
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: TargetFrameLowering(D, StackAl, LAO, TransAl) { }
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AMDGPUFrameLowering::~AMDGPUFrameLowering() { }
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unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const {
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// XXX: Hardcoding to 1 for now.
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//
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// I think the StackWidth should stored as metadata associated with the
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// MachineFunction. This metadata can either be added by a frontend, or
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// calculated by a R600 specific LLVM IR pass.
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//
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// The StackWidth determines how stack objects are laid out in memory.
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// For a vector stack variable, like: int4 stack[2], the data will be stored
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// in the following ways depending on the StackWidth.
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//
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// StackWidth = 1:
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//
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// T0.X = stack[0].x
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// T1.X = stack[0].y
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// T2.X = stack[0].z
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// T3.X = stack[0].w
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// T4.X = stack[1].x
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// T5.X = stack[1].y
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// T6.X = stack[1].z
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// T7.X = stack[1].w
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//
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// StackWidth = 2:
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//
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// T0.X = stack[0].x
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// T0.Y = stack[0].y
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// T1.X = stack[0].z
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// T1.Y = stack[0].w
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// T2.X = stack[1].x
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// T2.Y = stack[1].y
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// T3.X = stack[1].z
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// T3.Y = stack[1].w
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//
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// StackWidth = 4:
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// T0.X = stack[0].x
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// T0.Y = stack[0].y
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// T0.Z = stack[0].z
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// T0.W = stack[0].w
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// T1.X = stack[1].x
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// T1.Y = stack[1].y
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// T1.Z = stack[1].z
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// T1.W = stack[1].w
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return 1;
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}
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/// \returns The number of registers allocated for \p FI.
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int AMDGPUFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
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int FI) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Start the offset at 2 so we don't overwrite work group information.
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// XXX: We should only do this when the shader actually uses this
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// information.
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unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4);
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int UpperBound = FI == -1 ? MFI->getNumObjects() : FI;
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for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) {
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OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(i));
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OffsetBytes += MFI->getObjectSize(i);
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// Each register holds 4 bytes, so we must always align the offset to at
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// least 4 bytes, so that 2 frame objects won't share the same register.
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OffsetBytes = RoundUpToAlignment(OffsetBytes, 4);
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}
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if (FI != -1)
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OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(FI));
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return OffsetBytes / (getStackWidth(MF) * 4);
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}
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const TargetFrameLowering::SpillSlot *
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AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
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NumEntries = 0;
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return nullptr;
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}
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void
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AMDGPUFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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void
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AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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}
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bool
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AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const {
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return false;
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}
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