Craig Topper c41364cb4e [X86] Factor the core code out of LowerXALUO into a helper function. Use it in LowerBRCOND and LowerSELECT to avoid some duplicated code. ...

This makes it easier to keep the LowerBRCOND and LowerSELECT code in sync with LowerXALUO so they always pick the same operation for overflowing instructions.

This is inspired by the helper functions used by ARM and AArch64 for the same purpose.

The test change is because LowerSELECT was not in sync with LowerXALUO with regard to INC/DEC for SADDO/SSUBO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350198 91177308-0d34-0410-b5e6-96231b3b80d8

2019-01-01 19:34:11 +00:00

..

AArch64

Reversing the commit in revision 350186. Revision causes regression in 4

2019-01-01 07:28:55 +00:00

AMDGPU

[AMDGPU] Regenerate i64 shift tests.

2018-12-26 12:09:10 +00:00

ARC

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ARM

[ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR.

2018-12-21 18:07:10 +00:00

AVR

[AVR] Reorder the CHECK lines in directmem.ll to match current trunk

2018-11-09 23:17:59 +00:00

BPF

[BPF] Generate BTF DebugInfo under BPF target

2018-12-19 16:40:25 +00:00

Generic

Move llc-start-stop-instance to x86

2018-12-04 18:19:08 +00:00

Hexagon

[DAGCombiner] allow narrowing of add followed by truncate

2018-12-22 17:10:31 +00:00

Inputs

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Lanai

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

Mips

[MIPS GlobalISel] Select G_SELECT

2018-12-25 14:42:30 +00:00

MIR

[Dwarf/AArch64] Return address signing B key dwarf support

2018-12-21 10:45:08 +00:00

MSP430

[MSP430] Optimize srl/sra in case of A >> (8 + N)

2018-11-19 10:43:02 +00:00

Nios2

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NVPTX

[NVPTX] Allow libcalls that are defined in the current module.

2018-12-26 19:12:31 +00:00

PowerPC

[PowerPC] Fix machine verify pass error for PATCHPOINT pseudo instruction that bad machine code

2018-12-30 15:13:51 +00:00

RISCV

[RISCV] Add support for the various RISC-V FMA instruction variants

2018-12-13 10:49:05 +00:00

SPARC

[Sparc] Use float register for integer constrained with "f" in inline asm

2018-12-13 15:13:29 +00:00

SystemZ

[SystemZ] Make better use of VLLEZ

2018-12-20 13:05:03 +00:00

Thumb

[ARM] Complete the Thumb1 shift+and->shift+shift transforms.

2018-12-20 23:39:54 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Fix invalid machine instrs in -O0, verify in tests

2018-12-21 06:58:15 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Factor the core code out of LowerXALUO into a helper function. Use it in LowerBRCOND and LowerSELECT to avoid some duplicated code.

2019-01-01 19:34:11 +00:00

XCore

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00