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00e08fcaa0
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
4.3 KiB
C++
112 lines
4.3 KiB
C++
//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CriticalAntiDepBreaker class, which
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// implements register anti-dependence breaking along a blocks
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// critical path during post-RA scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
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#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
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#include "AntiDepBreaker.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include <map>
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namespace llvm {
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class RegisterClassInfo;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class CriticalAntiDepBreaker : public AntiDepBreaker {
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MachineFunction& MF;
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MachineRegisterInfo &MRI;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const RegisterClassInfo &RegClassInfo;
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/// AllocatableSet - The set of allocatable registers.
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/// We'll be ignoring anti-dependencies on non-allocatable registers,
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/// because they may not be safe to break.
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const BitVector AllocatableSet;
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/// Classes - For live regs that are only used in one register class in a
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/// live range, the register class. If the register is not live, the
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/// corresponding value is null. If the register is live but used in
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/// multiple register classes, the corresponding value is -1 casted to a
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/// pointer.
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std::vector<const TargetRegisterClass*> Classes;
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/// RegRefs - Map registers to all their references within a live range.
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std::multimap<unsigned, MachineOperand *> RegRefs;
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typedef std::multimap<unsigned, MachineOperand *>::const_iterator
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RegRefIter;
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/// KillIndices - The index of the most recent kill (proceeding bottom-up),
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/// or ~0u if the register is not live.
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std::vector<unsigned> KillIndices;
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/// DefIndices - The index of the most recent complete def (proceeding
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/// bottom up), or ~0u if the register is live.
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std::vector<unsigned> DefIndices;
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/// KeepRegs - A set of registers which are live and cannot be changed to
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/// break anti-dependencies.
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BitVector KeepRegs;
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public:
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CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo&);
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~CriticalAntiDepBreaker();
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/// Start - Initialize anti-dep breaking for a new basic block.
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void StartBlock(MachineBasicBlock *BB) override;
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/// BreakAntiDependencies - Identifiy anti-dependencies along the critical
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/// path
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/// of the ScheduleDAG and break them by renaming registers.
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///
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unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned InsertPosIndex,
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DbgValueVector &DbgValues) override;
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void Observe(MachineInstr *MI, unsigned Count,
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unsigned InsertPosIndex) override;
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/// Finish - Finish anti-dep breaking for a basic block.
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void FinishBlock() override;
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private:
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void PrescanInstruction(MachineInstr *MI);
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void ScanInstruction(MachineInstr *MI, unsigned Count);
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bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
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RegRefIter RegRefEnd,
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unsigned NewReg);
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unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
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RegRefIter RegRefEnd,
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unsigned AntiDepReg,
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unsigned LastNewReg,
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const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &Forbid);
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};
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}
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#endif
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