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f042d8480e
Summary:
Fix a case where the overflow value of type i1, which is legal on AVX512, was assigned to a VK1 register class.
We always want this value to be assigned to a GPR since the overflow return value is lowered to a SETO instruction.
Fixes pr30981.
Reviewers: mkuper, igorb, craig.topper, guyblank, qcolombet
Subscribers: qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D26620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286958 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
954 B
LLVM
32 lines
954 B
LLVM
; radr://6772169
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; RUN: llc < %s -fast-isel
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; PR30981
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; RUN: llc < %s -O0 -mcpu=x86-64 -mattr=+avx512f | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin10"
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%0 = type { i32, i1 } ; type %0
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declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
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define fastcc i32 @test() nounwind {
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entry:
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; CHECK-LABEL: test:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: addl $0, %eax
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; CHECK-NEXT: seto %cl
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
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; CHECK-NEXT: movb %cl, -{{[0-9]+}}(%rsp) ## 1-byte Spill
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; CHECK-NEXT: jo LBB0_2
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%tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
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%tmp2 = extractvalue %0 %tmp1, 1
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br i1 %tmp2, label %.backedge, label %BB3
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BB3:
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%tmp4 = extractvalue %0 %tmp1, 0
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br label %.backedge
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.backedge:
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ret i32 0
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}
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