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a466b368fe
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
| \ / |
| X |
| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295223 91177308-0d34-0410-b5e6-96231b3b80d8
558 lines
15 KiB
LLVM
558 lines
15 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
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declare void @bar(i32)
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declare void @car(i32)
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declare void @dar(i32)
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declare void @ear(i32)
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declare void @far(i32)
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declare i1 @qux()
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@GHJK = global i32 0
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@HABC = global i32 0
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; BranchFolding should tail-merge the stores since they all precede
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; direct branches to the same place.
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; CHECK-LABEL: tail_merge_me:
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; CHECK-NOT: GHJK
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: movl $1, HABC(%rip)
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; CHECK-NOT: GHJK
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define void @tail_merge_me() nounwind {
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entry:
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%a = call i1 @qux()
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br i1 %a, label %A, label %next
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next:
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%b = call i1 @qux()
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br i1 %b, label %B, label %C
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A:
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call void @bar(i32 0)
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store i32 0, i32* @GHJK
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br label %M
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B:
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call void @car(i32 1)
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store i32 0, i32* @GHJK
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br label %M
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C:
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call void @dar(i32 2)
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store i32 0, i32* @GHJK
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br label %M
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M:
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store i32 1, i32* @HABC
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%c = call i1 @qux()
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br i1 %c, label %return, label %altret
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return:
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call void @ear(i32 1000)
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ret void
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altret:
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call void @far(i32 1001)
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ret void
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}
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declare i8* @choose(i8*, i8*)
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; BranchFolding should tail-duplicate the indirect jump to avoid
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; redundant branching.
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; CHECK-LABEL: tail_duplicate_me:
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%r
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%r
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%r
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define void @tail_duplicate_me() nounwind {
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entry:
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%a = call i1 @qux()
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%c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
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i8* blockaddress(@tail_duplicate_me, %altret))
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br i1 %a, label %A, label %next
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next:
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%b = call i1 @qux()
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br i1 %b, label %B, label %C
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A:
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call void @bar(i32 0)
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store i32 0, i32* @GHJK
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br label %M
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B:
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call void @car(i32 1)
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store i32 0, i32* @GHJK
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br label %M
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C:
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call void @dar(i32 2)
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store i32 0, i32* @GHJK
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br label %M
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M:
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indirectbr i8* %c, [label %return, label %altret]
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return:
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call void @ear(i32 1000)
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ret void
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altret:
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call void @far(i32 1001)
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ret void
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}
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; BranchFolding shouldn't try to merge the tails of two blocks
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; with only a branch in common, regardless of the fallthrough situation.
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; CHECK-LABEL: dont_merge_oddly:
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; CHECK-NOT: ret
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; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
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; CHECK-NEXT: jbe .LBB2_3
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; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
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; CHECK-NEXT: ja .LBB2_4
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_3:
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; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
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; CHECK-NEXT: jbe .LBB2_2
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; CHECK-NEXT: .LBB2_4:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: ret
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define i1 @dont_merge_oddly(float* %result) nounwind {
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entry:
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%tmp4 = getelementptr float, float* %result, i32 2
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%tmp5 = load float, float* %tmp4, align 4
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%tmp7 = getelementptr float, float* %result, i32 4
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%tmp8 = load float, float* %tmp7, align 4
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%tmp10 = getelementptr float, float* %result, i32 6
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%tmp11 = load float, float* %tmp10, align 4
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%tmp12 = fcmp olt float %tmp8, %tmp11
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br i1 %tmp12, label %bb, label %bb21
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bb:
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%tmp23469 = fcmp olt float %tmp5, %tmp8
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br i1 %tmp23469, label %bb26, label %bb30
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bb21:
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%tmp23 = fcmp olt float %tmp5, %tmp11
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br i1 %tmp23, label %bb26, label %bb30
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bb26:
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ret i1 0
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bb30:
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ret i1 1
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}
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; Do any-size tail-merging when two candidate blocks will both require
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; an unconditional jump to complete a two-way conditional branch.
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; CHECK-LABEL: c_expand_expr_stmt:
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;
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; This test only works when register allocation happens to use %rax for both
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; load addresses.
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;
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; CHE: jmp .LBB3_11
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; CHE-NEXT: .LBB3_9:
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; CHE-NEXT: movq 8(%rax), %rax
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; CHE-NEXT: xorl %edx, %edx
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; CHE-NEXT: movb 16(%rax), %al
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; CHE-NEXT: cmpb $16, %al
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; CHE-NEXT: je .LBB3_11
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; CHE-NEXT: cmpb $23, %al
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; CHE-NEXT: jne .LBB3_14
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; CHE-NEXT: .LBB3_11:
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%0 = type { %struct.rtx_def* }
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%struct.lang_decl = type opaque
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%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] }
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%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* }
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%union..2anon = type { i32 }
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%union.rtunion = type { i8* }
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%union.tree_node = type { %struct.tree_decl }
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define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
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entry:
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%tmp4 = load i8, i8* null, align 8 ; <i8> [#uses=3]
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switch i8 %tmp4, label %bb3 [
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i8 18, label %bb
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]
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bb: ; preds = %entry
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switch i32 undef, label %bb1 [
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i32 0, label %bb2.i
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i32 37, label %bb.i
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]
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bb.i: ; preds = %bb
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switch i32 undef, label %bb1 [
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i32 0, label %lvalue_p.exit
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]
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bb2.i: ; preds = %bb
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br label %bb3
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lvalue_p.exit: ; preds = %bb.i
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%tmp21 = load %union.tree_node*, %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3]
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%tmp22 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
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%tmp23 = load i8, i8* %tmp22, align 8 ; <i8> [#uses=1]
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%tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1]
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switch i32 %tmp24, label %lvalue_p.exit4 [
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i32 0, label %bb2.i3
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i32 2, label %bb.i1
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]
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bb.i1: ; preds = %lvalue_p.exit
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%tmp25 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
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%tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp27 = load %union.tree_node*, %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
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%tmp28 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp29 = load i8, i8* %tmp28, align 8 ; <i8> [#uses=1]
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%tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1]
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switch i32 %tmp30, label %lvalue_p.exit4 [
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i32 0, label %bb2.i.i2
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i32 2, label %bb.i.i
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]
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bb.i.i: ; preds = %bb.i1
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%tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1]
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%phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1]
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br label %lvalue_p.exit4
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bb2.i.i2: ; preds = %bb.i1
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%tmp35 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
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%tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp37 = load %union.tree_node*, %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
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%tmp38 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp39 = load i8, i8* %tmp38, align 8 ; <i8> [#uses=1]
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switch i8 %tmp39, label %bb2 [
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i8 16, label %lvalue_p.exit4
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i8 23, label %lvalue_p.exit4
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]
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bb2.i3: ; preds = %lvalue_p.exit
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%tmp40 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
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%tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp42 = load %union.tree_node*, %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
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%tmp43 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp44 = load i8, i8* %tmp43, align 8 ; <i8> [#uses=1]
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switch i8 %tmp44, label %bb2 [
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i8 16, label %lvalue_p.exit4
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i8 23, label %lvalue_p.exit4
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]
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lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit
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%tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1]
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%tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1]
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%or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1]
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br i1 %or.cond, label %bb2, label %bb3
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bb1: ; preds = %bb2.i.i, %bb.i, %bb
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%.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1]
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br i1 %.old, label %bb2, label %bb3
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bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2
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br label %bb3
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bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry
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%expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0]
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unreachable
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}
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declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly
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declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
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; If one tail merging candidate falls through into the other,
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; tail merging is likely profitable regardless of how few
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; instructions are involved. This function should have only
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; one ret instruction.
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; CHECK-LABEL: foo:
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; CHECK: callq func
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; CHECK-NEXT: popq
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ret
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define void @foo(i1* %V) nounwind {
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entry:
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%t0 = icmp eq i1* %V, null
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br i1 %t0, label %return, label %bb
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bb:
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call void @func()
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ret void
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return:
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ret void
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}
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declare void @func()
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; one - One instruction may be tail-duplicated even with optsize.
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; CHECK-LABEL: one:
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; CHECK: j{{.*}} tail_call_me
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; CHECK: j{{.*}} tail_call_me
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@XYZ = external global i32
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declare void @tail_call_me()
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define void @one(i32 %v) nounwind optsize {
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entry:
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%0 = icmp eq i32 %v, 0
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br i1 %0, label %bbx, label %bby
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bby:
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switch i32 %v, label %bb7 [
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i32 16, label %return
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]
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bb7:
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tail call void @tail_call_me()
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ret void
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bbx:
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switch i32 %v, label %bb12 [
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i32 128, label %return
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]
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bb12:
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tail call void @tail_call_me()
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ret void
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return:
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ret void
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}
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; two - Same as one, but with two instructions in the common
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; tail instead of one. This is too much to be merged, given
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; the optsize attribute.
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; CHECK-LABEL: two:
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; CHECK-NOT: XYZ
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; CHECK: ret
|
|
; CHECK: movl $0, XYZ(%rip)
|
|
; CHECK: movl $1, XYZ(%rip)
|
|
; CHECK-NOT: XYZ
|
|
|
|
define void @two() nounwind optsize {
|
|
entry:
|
|
%0 = icmp eq i32 undef, 0
|
|
br i1 %0, label %bbx, label %bby
|
|
|
|
bby:
|
|
switch i32 undef, label %bb7 [
|
|
i32 16, label %return
|
|
]
|
|
|
|
bb7:
|
|
store volatile i32 0, i32* @XYZ
|
|
store volatile i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
bbx:
|
|
switch i32 undef, label %bb12 [
|
|
i32 128, label %return
|
|
]
|
|
|
|
bb12:
|
|
store volatile i32 0, i32* @XYZ
|
|
store volatile i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
return:
|
|
ret void
|
|
}
|
|
|
|
; two_minsize - Same as two, but with minsize instead of optsize.
|
|
|
|
; CHECK-LABEL: two_minsize:
|
|
; CHECK-NOT: XYZ
|
|
; CHECK: ret
|
|
; CHECK: andl $0, XYZ(%rip)
|
|
; CHECK: movl $1, XYZ(%rip)
|
|
; CHECK-NOT: XYZ
|
|
|
|
define void @two_minsize() nounwind minsize {
|
|
entry:
|
|
%0 = icmp eq i32 undef, 0
|
|
br i1 %0, label %bbx, label %bby
|
|
|
|
bby:
|
|
switch i32 undef, label %bb7 [
|
|
i32 16, label %return
|
|
]
|
|
|
|
bb7:
|
|
store volatile i32 0, i32* @XYZ
|
|
store volatile i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
bbx:
|
|
switch i32 undef, label %bb12 [
|
|
i32 128, label %return
|
|
]
|
|
|
|
bb12:
|
|
store volatile i32 0, i32* @XYZ
|
|
store volatile i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
return:
|
|
ret void
|
|
}
|
|
|
|
; two_nosize - Same as two, but without the optsize attribute.
|
|
; Now two instructions are enough to be tail-duplicated.
|
|
|
|
; CHECK-LABEL: two_nosize:
|
|
; CHECK: movl $0, XYZ(%rip)
|
|
; CHECK: jmp tail_call_me
|
|
; CHECK: movl $0, XYZ(%rip)
|
|
; CHECK: jmp tail_call_me
|
|
|
|
define void @two_nosize() nounwind {
|
|
entry:
|
|
%0 = icmp eq i32 undef, 0
|
|
br i1 %0, label %bbx, label %bby
|
|
|
|
bby:
|
|
switch i32 undef, label %bb7 [
|
|
i32 16, label %return
|
|
]
|
|
|
|
bb7:
|
|
store volatile i32 0, i32* @XYZ
|
|
tail call void @tail_call_me()
|
|
ret void
|
|
|
|
bbx:
|
|
switch i32 undef, label %bb12 [
|
|
i32 128, label %return
|
|
]
|
|
|
|
bb12:
|
|
store volatile i32 0, i32* @XYZ
|
|
tail call void @tail_call_me()
|
|
ret void
|
|
|
|
return:
|
|
ret void
|
|
}
|
|
|
|
; Tail-merging should merge the two ret instructions since one side
|
|
; can fall-through into the ret and the other side has to branch anyway.
|
|
|
|
; CHECK-LABEL: TESTE:
|
|
; CHECK: ret
|
|
; CHECK-NOT: ret
|
|
; CHECK: size TESTE
|
|
|
|
define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
|
|
entry:
|
|
%cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1]
|
|
%varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1]
|
|
%cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1]
|
|
br i1 %cmp410, label %for.end, label %bb.nph
|
|
|
|
bb.nph: ; preds = %entry
|
|
%tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1]
|
|
ret i64 %tmp15
|
|
|
|
for.end: ; preds = %entry
|
|
ret i64 %varx.0
|
|
}
|
|
|
|
; We should tail merge small blocks that don't end in a tail call or return
|
|
; instruction. Those blocks are typically unreachable and will be placed
|
|
; out-of-line after the main return, so we should try to eliminate as many of
|
|
; them as possible.
|
|
|
|
; CHECK-LABEL: merge_aborts:
|
|
; CHECK-NOT: callq abort
|
|
; CHECK: ret
|
|
; CHECK: callq abort
|
|
; CHECK-NOT: callq abort
|
|
; CHECK: .Lfunc_end{{.*}}:
|
|
|
|
declare void @abort()
|
|
define void @merge_aborts() {
|
|
entry:
|
|
%c1 = call i1 @qux()
|
|
br i1 %c1, label %cont1, label %abort1
|
|
abort1:
|
|
call void @abort()
|
|
unreachable
|
|
cont1:
|
|
%c2 = call i1 @qux()
|
|
br i1 %c2, label %cont2, label %abort2
|
|
abort2:
|
|
call void @abort()
|
|
unreachable
|
|
cont2:
|
|
%c3 = call i1 @qux()
|
|
br i1 %c3, label %cont3, label %abort3
|
|
abort3:
|
|
call void @abort()
|
|
unreachable
|
|
cont3:
|
|
%c4 = call i1 @qux()
|
|
br i1 %c4, label %cont4, label %abort4
|
|
abort4:
|
|
call void @abort()
|
|
unreachable
|
|
cont4:
|
|
ret void
|
|
}
|
|
|
|
; Use alternating abort functions so that the blocks we wish to merge are not
|
|
; layout successors during branch folding.
|
|
|
|
; CHECK-LABEL: merge_alternating_aborts:
|
|
; CHECK-NOT: callq abort
|
|
; CHECK: ret
|
|
; CHECK: callq abort
|
|
; CHECK: callq alt_abort
|
|
; CHECK-NOT: callq abort
|
|
; CHECK-NOT: callq alt_abort
|
|
; CHECK: .Lfunc_end{{.*}}:
|
|
|
|
declare void @alt_abort()
|
|
|
|
define void @merge_alternating_aborts() {
|
|
entry:
|
|
%c1 = call i1 @qux()
|
|
br i1 %c1, label %cont1, label %abort1
|
|
abort1:
|
|
call void @abort()
|
|
unreachable
|
|
cont1:
|
|
%c2 = call i1 @qux()
|
|
br i1 %c2, label %cont2, label %abort2
|
|
abort2:
|
|
call void @alt_abort()
|
|
unreachable
|
|
cont2:
|
|
%c3 = call i1 @qux()
|
|
br i1 %c3, label %cont3, label %abort3
|
|
abort3:
|
|
call void @abort()
|
|
unreachable
|
|
cont3:
|
|
%c4 = call i1 @qux()
|
|
br i1 %c4, label %cont4, label %abort4
|
|
abort4:
|
|
call void @alt_abort()
|
|
unreachable
|
|
cont4:
|
|
ret void
|
|
}
|