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commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155047 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
4.4 KiB
C++
130 lines
4.4 KiB
C++
//===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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// This pass tries to provide opportunities for better optimization of muxes.
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// The default code generated for something like: flag = (a == b) ? 1 : 3;
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// would be:
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//
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// {p0 = cmp.eq(r0,r1)}
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// {r3 = mux(p0,#1,#3)}
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//
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// This requires two packets. If we use .new predicated immediate transfers,
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// then we can do this in a single packet, e.g.:
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//
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// {p0 = cmp.eq(r0,r1)
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// if (p0.new) r3 = #1
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// if (!p0.new) r3 = #3}
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//
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// Note that the conditional assignments are not generated in .new form here.
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// We assume opptimisically that they will be formed later.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "xfer"
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#include "HexagonTargetMachine.h"
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#include "HexagonSubtarget.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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class HexagonSplitTFRCondSets : public MachineFunctionPass {
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HexagonTargetMachine& QTM;
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const HexagonSubtarget &QST;
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public:
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static char ID;
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HexagonSplitTFRCondSets(HexagonTargetMachine& TM) :
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MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
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const char *getPassName() const {
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return "Hexagon Split TFRCondSets";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char HexagonSplitTFRCondSets::ID = 0;
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bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
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const TargetInstrInfo *TII = QTM.getInstrInfo();
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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// Traverse the basic block.
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for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
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++MII) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::TFR_condset_rr) {
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int DestReg = MI->getOperand(0).getReg();
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int SrcReg1 = MI->getOperand(2).getReg();
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int SrcReg2 = MI->getOperand(3).getReg();
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// Minor optimization: do not emit the predicated copy if the source and
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// the destination is the same register
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if (DestReg != SrcReg1) {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cPt),
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DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
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}
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if (DestReg != SrcReg2) {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cNotPt),
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DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
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}
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::TFR_condset_ii) {
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int DestReg = MI->getOperand(0).getReg();
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int SrcReg1 = MI->getOperand(1).getReg();
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int Immed1 = MI->getOperand(2).getImm();
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int Immed2 = MI->getOperand(3).getImm();
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cPt),
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DestReg).addReg(SrcReg1).addImm(Immed1);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cNotPt),
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DestReg).addReg(SrcReg1).addImm(Immed2);
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MII = MBB->erase(MI);
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--MII;
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}
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}
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}
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return true;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *llvm::createHexagonSplitTFRCondSets(HexagonTargetMachine &TM) {
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return new HexagonSplitTFRCondSets(TM);
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}
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