Matt Arsenault 8a70e28114 R600/SI: Don't move operands that are required to be SGPRs ... e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218529 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-26 17:54:52 +00:00
..
AArch64	Revert patch of r218493, delete the test case	2014-09-26 02:40:54 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Fix crash with an insertvalue that produces an empty object.	2014-09-20 00:10:47 +00:00
Hexagon	Add missing attributes !cmp.[eq,gt,gtu] instructions.	2014-09-25 13:09:54 +00:00
Inputs
Mips	Add the first backend support for on demand subtarget creation	2014-09-26 01:44:08 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	[Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate	2014-09-23 20:46:49 +00:00
R600	R600/SI: Don't move operands that are required to be SGPRs	2014-09-26 17:54:52 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] In the new vector shuffle lowering, when trying to do another	2014-09-26 17:24:26 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00