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8bc6721525
Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions. Reviewed by Simon Dardis Differential: D32286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301394 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.6 KiB
C++
103 lines
3.6 KiB
C++
//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
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cl::desc("Always use $gp as the global base register."));
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MipsFunctionInfo::~MipsFunctionInfo() = default;
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bool MipsFunctionInfo::globalBaseRegSet() const {
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return GlobalBaseReg;
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}
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unsigned MipsFunctionInfo::getGlobalBaseReg() {
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// Return if it has already been initialized.
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if (GlobalBaseReg)
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return GlobalBaseReg;
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MipsSubtarget const &STI =
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static_cast<const MipsSubtarget &>(MF.getSubtarget());
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const TargetRegisterClass *RC =
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STI.inMips16Mode()
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? &Mips::CPU16RegsRegClass
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: static_cast<const MipsTargetMachine &>(MF.getTarget())
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.getABI()
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.IsN64()
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? &Mips::GPR64RegClass
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: &Mips::GPR32RegClass;
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return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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void MipsFunctionInfo::createEhDataRegsFI() {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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for (int I = 0; I < 4; ++I) {
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const TargetRegisterClass &RC =
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static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
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? Mips::GPR64RegClass
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: Mips::GPR32RegClass;
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EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
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TRI.getSpillAlignment(RC), false);
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}
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}
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void MipsFunctionInfo::createISRRegFI() {
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// ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
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// The current implementation only supports Mips32r2+ not Mips64rX. Status
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// is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
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// however Mips32r2+ is the supported architecture.
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const TargetRegisterClass &RC = Mips::GPR32RegClass;
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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for (int I = 0; I < 2; ++I)
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ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
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TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
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}
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bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
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return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
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|| FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
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}
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bool MipsFunctionInfo::isISRRegFI(int FI) const {
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return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
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return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) {
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return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
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}
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int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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if (MoveF64ViaSpillFI == -1) {
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MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
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TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
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}
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return MoveF64ViaSpillFI;
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}
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void MipsFunctionInfo::anchor() {}
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