Nate Begeman 8d94832394 Woo, it kinda works. We now generate this atrociously bad, but correct, ...

code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-19 01:12:32 +00:00

..

Alpha

This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

2005-10-09 20:11:35 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Fix CodeGen/Generic/bool-to-double.ll

2005-10-07 04:50:48 +00:00

PowerPC

Woo, it kinda works. We now generate this atrociously bad, but correct,

2005-10-19 01:12:32 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

silence a warning

2005-10-02 16:27:59 +00:00

X86

Remove some dead code now that the dag combiner exists.

2005-10-15 22:08:02 +00:00

Makefile

Implement the --enable-targets= feature of the configure script. The make

2005-04-22 17:20:11 +00:00

MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Pull DAG ISel generation nodes out of the PowerPC backend to where they

2005-10-10 06:00:30 +00:00

TargetData.cpp

Update to use the new MathExtras.h support for log2 computation.

2005-08-02 19:26:06 +00:00

TargetFrameInfo.cpp

Eliminate all remaining tabs and trailing spaces.

2005-07-27 06:12:32 +00:00

TargetInstrInfo.cpp

Convert tabs to spaces

2005-04-22 17:54:37 +00:00

TargetMachine.cpp

Remove the X86 and PowerPC Simple instruction selectors; their time has

2005-08-18 23:53:15 +00:00

TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

Convert tabs to spaces

2005-04-22 17:54:37 +00:00

TargetSchedule.td

Checking in first round of scheduling tablegen files. Not tied in as yet.

2005-10-18 16:23:40 +00:00

TargetSelectionDAG.td

add the integer truncate/extension operations

2005-10-14 06:40:20 +00:00

TargetSubtarget.cpp

Eliminate all remaining tabs and trailing spaces.

2005-07-27 06:12:32 +00:00