Reid Kleckner a83ebc9d3b Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each ...

Now X86ISelLowering doesn't depend on many IR analyses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375320 91177308-0d34-0410-b5e6-96231b3b80d8

2019-10-19 01:31:09 +00:00

..

CMakeLists.txt

Remove trailing whitespace to trigger re-cmaking

2017-10-02 21:54:38 +00:00

DAGCombiner.cpp

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

FastISel.cpp

[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field

2019-10-15 10:46:24 +00:00

FunctionLoweringInfo.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

InstrEmitter.cpp

[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field

2019-10-15 10:46:24 +00:00

InstrEmitter.h

[SelectionDAG] Enhance the simplification of copyto from implicit-def.

2019-05-27 18:26:29 +00:00

LegalizeDAG.cpp

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

LegalizeFloatTypes.cpp

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeIntegerTypes.cpp

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

LegalizeTypes.cpp

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeTypes.h

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

LegalizeTypesGeneric.cpp

[LegalizeTypes][X86] When splitting a vselect for type legalization, don't split a setcc condition if the setcc input is legal and vXi1 conditions are supported

2019-10-06 18:43:03 +00:00

LegalizeVectorOps.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

LegalizeVectorTypes.cpp

[LegalizeTypes] Don't use PromoteTargetBoolean in WidenVecOp_SETCC.

2019-10-16 03:29:24 +00:00

LLVMBuild.txt

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

ResourcePriorityQueue.cpp

Implementation of asm-goto support in LLVM

2019-02-08 20:48:56 +00:00

ScheduleDAGFast.cpp

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

2019-08-01 23:27:28 +00:00

ScheduleDAGRRList.cpp

[ScheduleDAG] When a node is cloned, add an edge between the nodes.

2019-10-04 19:51:40 +00:00

ScheduleDAGSDNodes.cpp

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

ScheduleDAGSDNodes.h

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

ScheduleDAGVLIW.cpp

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

SDNodeDbgValue.h

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

SelectionDAG.cpp

[FPEnv] Add constrained intrinsics for lrint and lround

2019-10-07 13:20:00 +00:00

SelectionDAGAddressAnalysis.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

SelectionDAGBuilder.cpp

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

SelectionDAGBuilder.h

[llvm] Migrate llvm::make_unique to std::make_unique

2019-08-15 15:54:37 +00:00

SelectionDAGDumper.cpp

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

SelectionDAGISel.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

SelectionDAGPrinter.cpp

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

SelectionDAGTargetInfo.cpp

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

StatepointLowering.cpp

[Statepoints] Fix overalignment of loads in no-realign-stack functions

2019-08-02 20:17:37 +00:00

StatepointLowering.h

[FastISel] Fix crash for gc.relocate lowring

2019-04-05 05:41:08 +00:00

TargetLowering.cpp

[DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863)

2019-10-01 15:32:04 +00:00