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8f2a85e099
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
4.3 KiB
LLVM
90 lines
4.3 KiB
LLVM
; RUN: llc -march=cpp -o - %s | FileCheck %s
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define void @test_atomicrmw(i32* %addr, i32 %inc) {
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%inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread
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; CHECK: [[INST]]->setName("inst0");
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; CHECK: [[INST]]->setVolatile(false);
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%inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread
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; CHECK: [[INST]]->setName("inst1");
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; CHECK: [[INST]]->setVolatile(false);
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%inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread
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; CHECK: [[INST]]->setName("inst2");
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; CHECK: [[INST]]->setVolatile(true);
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%inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread
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; CHECK: [[INST]]->setName("inst3");
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; CHECK: [[INST]]->setVolatile(false);
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%inst4 = atomicrmw nand i32* %addr, i32 %inc release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread
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; CHECK: [[INST]]->setName("inst4");
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; CHECK: [[INST]]->setVolatile(false);
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%inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread
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; CHECK: [[INST]]->setName("inst5");
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; CHECK: [[INST]]->setVolatile(true);
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%inst6 = atomicrmw xor i32* %addr, i32 %inc release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread
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; CHECK: [[INST]]->setName("inst6");
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; CHECK: [[INST]]->setVolatile(false);
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%inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread
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; CHECK: [[INST]]->setName("inst7");
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; CHECK: [[INST]]->setVolatile(true);
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%inst8 = atomicrmw min i32* %addr, i32 %inc acquire
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread
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; CHECK: [[INST]]->setName("inst8");
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; CHECK: [[INST]]->setVolatile(false);
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%inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread
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; CHECK: [[INST]]->setName("inst9");
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; CHECK: [[INST]]->setVolatile(true);
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%inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
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; CHECK: [[INST]]->setName("inst10");
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; CHECK: [[INST]]->setVolatile(false);
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ret void
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}
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define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
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%inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
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; CHECK: [[INST]]->setName("inst0");
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; CHECK: [[INST]]->setVolatile(false);
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; CHECK: [[INST]]->setWeak(false);
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%inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
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; CHECK: [[INST]]->setName("inst1");
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; CHECK: [[INST]]->setVolatile(true);
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; CHECK: [[INST]]->setWeak(false);
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%inst2 = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
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; CHECK: [[INST]]->setName("inst2");
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; CHECK: [[INST]]->setVolatile(false);
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; CHECK: [[INST]]->setWeak(true);
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%inst3 = cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
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; CHECK: [[INST]]->setName("inst3");
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; CHECK: [[INST]]->setVolatile(true);
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; CHECK: [[INST]]->setWeak(true);
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ret void
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}
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