Francis Visoiu Mistrih a4ec08b6fd [CodeGen] Print register names in lowercase in both MIR and debug output ...

As part of the unification of the debug format and the MIR format,
always print registers as lowercase.

* Only debug printing is affected. It now follows MIR.

Differential Revision: https://reviews.llvm.org/D40417

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319187 91177308-0d34-0410-b5e6-96231b3b80d8

2017-11-28 17:15:09 +00:00

..

add.ll

Reland "[mips] Fix multiprecision arithmetic."

2017-07-13 11:28:05 +00:00

addrspacecast.ll

[mips] Reserve address spaces 1-255 for software use.

2015-09-08 09:07:03 +00:00

and.ll

[DAG] combine assertsexts around a trunc

2017-10-09 15:22:20 +00:00

ashr.ll

CodeGen: BlockPlacement: Reduce TriangleChainCount to 2

2017-03-16 01:32:29 +00:00

atomicrmx.ll

[mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes.

2015-11-06 12:07:20 +00:00

call.ll

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

extractelement.ll

[DAG] Do MergeConsecutiveStores again before Instruction Selection

2017-11-27 15:28:15 +00:00

indirectbr.ll

[mips] Correct label prefixes for N32 and N64.

2016-07-19 10:49:03 +00:00

lh_lhu.ll

[mips] Don't derive the default ABI from the CPU in the backend.

2016-06-23 12:42:53 +00:00

load-atomic.ll

[mips] Use --check-prefixes where appropriate. NFC.

2016-06-24 12:23:17 +00:00

lshr.ll

CodeGen: BlockPlacement: Reduce TriangleChainCount to 2

2017-03-16 01:32:29 +00:00

mul.ll

Revert "[mips] Reordering callseq* nodes to be linear"

2017-10-20 14:35:41 +00:00

not.ll

[DAG] combine assertsexts around a trunc

2017-10-09 15:22:20 +00:00

or.ll

[DAG] combine assertsexts around a trunc

2017-10-09 15:22:20 +00:00

ret.ll

[mips] Optimize materialization of i64 constants

2016-07-25 09:57:28 +00:00

sdiv.ll

Revert "[mips] Reordering callseq* nodes to be linear"

2017-10-20 14:35:41 +00:00

select-dbl.ll

Reland r308585

2017-07-20 13:08:18 +00:00

select-flt.ll

Reland r308585

2017-07-20 13:08:18 +00:00

select-int.ll

[mips] interAptiv based generic schedule model

2016-09-01 14:53:53 +00:00

shl.ll

CodeGen: BlockPlacement: Reduce TriangleChainCount to 2

2017-03-16 01:32:29 +00:00

sqrt.ll

[mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backend

2015-10-06 15:17:25 +00:00

srem.ll

Revert "[mips] Reordering callseq* nodes to be linear"

2017-10-20 14:35:41 +00:00

store-atomic.ll

[mips] Use --check-prefixes where appropriate. NFC.

2016-06-24 12:23:17 +00:00

sub.ll

[mips] Use the delay slot filler to convert branches for microMIPSR6.

2017-11-23 12:38:04 +00:00

udiv.ll

Revert "[mips] Reordering callseq* nodes to be linear"

2017-10-20 14:35:41 +00:00

urem.ll

Revert "[mips] Reordering callseq* nodes to be linear"

2017-10-20 14:35:41 +00:00

xor.ll

[DAG] combine assertsexts around a trunc

2017-10-09 15:22:20 +00:00