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0673379712
Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188592 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.1 KiB
LLVM
52 lines
1.1 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
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define i32 @shl() nounwind ssp {
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entry:
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; ARM: shl
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; ARM: lsl r0, r0, #2
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%shl = shl i32 -1, 2
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ret i32 %shl
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}
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define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: shl_reg
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; ARM: lsl r0, r0, r1
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%shl = shl i32 %src1, %src2
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ret i32 %shl
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}
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define i32 @lshr() nounwind ssp {
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entry:
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; ARM: lshr
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; ARM: lsr r0, r0, #2
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%lshr = lshr i32 -1, 2
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ret i32 %lshr
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}
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define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: lshr_reg
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; ARM: lsr r0, r0, r1
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%lshr = lshr i32 %src1, %src2
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ret i32 %lshr
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}
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define i32 @ashr() nounwind ssp {
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entry:
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; ARM: ashr
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; ARM: asr r0, r0, #2
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%ashr = ashr i32 -1, 2
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ret i32 %ashr
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}
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define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: ashr_reg
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; ARM: asr r0, r0, r1
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%ashr = ashr i32 %src1, %src2
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ret i32 %ashr
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}
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