Craig Topper 95717dbb11 [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't. ... Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present. Fixes PR21169. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219194 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-07 07:29:50 +00:00
..
AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Thumb2 M-class MSR instruction support changes	2014-09-01 11:25:07 +00:00
Mips	[mips] Fix disassembly of [ls][wd]c[23], cache, and pref	2014-10-01 08:26:55 +00:00
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
Sparc
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	[X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't.	2014-10-07 07:29:50 +00:00
XCore