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272458bd06
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186725 91177308-0d34-0410-b5e6-96231b3b80d8
536 lines
18 KiB
C++
536 lines
18 KiB
C++
//===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass compute turns all control flow pseudo instructions into native one
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/// computing their address on the fly ; it also sets STACK_SIZE info.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "r600cf"
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#include "llvm/Support/Debug.h"
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class R600ControlFlowFinalizer : public MachineFunctionPass {
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private:
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typedef std::pair<MachineInstr *, std::vector<MachineInstr *> > ClauseFile;
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enum ControlFlowInstruction {
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CF_TC,
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CF_VC,
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CF_CALL_FS,
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CF_WHILE_LOOP,
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CF_END_LOOP,
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CF_LOOP_BREAK,
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CF_LOOP_CONTINUE,
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CF_JUMP,
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CF_ELSE,
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CF_POP,
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CF_END
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};
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static char ID;
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const R600InstrInfo *TII;
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const R600RegisterInfo *TRI;
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unsigned MaxFetchInst;
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const AMDGPUSubtarget &ST;
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bool IsTrivialInst(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::KILL:
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case AMDGPU::RETURN:
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return true;
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default:
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return false;
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}
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}
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const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const {
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unsigned Opcode = 0;
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bool isEg = (ST.getGeneration() >= AMDGPUSubtarget::EVERGREEN);
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switch (CFI) {
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case CF_TC:
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Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
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break;
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case CF_VC:
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Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600;
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break;
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case CF_CALL_FS:
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Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600;
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break;
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case CF_WHILE_LOOP:
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Opcode = isEg ? AMDGPU::WHILE_LOOP_EG : AMDGPU::WHILE_LOOP_R600;
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break;
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case CF_END_LOOP:
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Opcode = isEg ? AMDGPU::END_LOOP_EG : AMDGPU::END_LOOP_R600;
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break;
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case CF_LOOP_BREAK:
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Opcode = isEg ? AMDGPU::LOOP_BREAK_EG : AMDGPU::LOOP_BREAK_R600;
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break;
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case CF_LOOP_CONTINUE:
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Opcode = isEg ? AMDGPU::CF_CONTINUE_EG : AMDGPU::CF_CONTINUE_R600;
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break;
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case CF_JUMP:
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Opcode = isEg ? AMDGPU::CF_JUMP_EG : AMDGPU::CF_JUMP_R600;
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break;
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case CF_ELSE:
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Opcode = isEg ? AMDGPU::CF_ELSE_EG : AMDGPU::CF_ELSE_R600;
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break;
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case CF_POP:
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Opcode = isEg ? AMDGPU::POP_EG : AMDGPU::POP_R600;
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break;
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case CF_END:
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if (ST.hasCaymanISA()) {
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Opcode = AMDGPU::CF_END_CM;
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break;
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}
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Opcode = isEg ? AMDGPU::CF_END_EG : AMDGPU::CF_END_R600;
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break;
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}
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assert (Opcode && "No opcode selected");
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return TII->get(Opcode);
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}
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bool isCompatibleWithClause(const MachineInstr *MI,
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std::set<unsigned> &DstRegs) const {
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unsigned DstMI, SrcMI;
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for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
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E = MI->operands_end(); I != E; ++I) {
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const MachineOperand &MO = *I;
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if (!MO.isReg())
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continue;
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if (MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (AMDGPU::R600_Reg128RegClass.contains(Reg))
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DstMI = Reg;
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else
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DstMI = TRI->getMatchingSuperReg(Reg,
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TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
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&AMDGPU::R600_Reg128RegClass);
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}
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if (MO.isUse()) {
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unsigned Reg = MO.getReg();
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if (AMDGPU::R600_Reg128RegClass.contains(Reg))
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SrcMI = Reg;
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else
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SrcMI = TRI->getMatchingSuperReg(Reg,
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TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
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&AMDGPU::R600_Reg128RegClass);
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}
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}
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if ((DstRegs.find(SrcMI) == DstRegs.end())) {
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DstRegs.insert(DstMI);
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return true;
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} else
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return false;
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}
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ClauseFile
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MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
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const {
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MachineBasicBlock::iterator ClauseHead = I;
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std::vector<MachineInstr *> ClauseContent;
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unsigned AluInstCount = 0;
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bool IsTex = TII->usesTextureCache(ClauseHead);
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std::set<unsigned> DstRegs;
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for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
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if (IsTrivialInst(I))
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continue;
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if (AluInstCount >= MaxFetchInst)
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break;
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if ((IsTex && !TII->usesTextureCache(I)) ||
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(!IsTex && !TII->usesVertexCache(I)))
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break;
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if (!isCompatibleWithClause(I, DstRegs))
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break;
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AluInstCount ++;
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ClauseContent.push_back(I);
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}
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MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
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getHWInstrDesc(IsTex?CF_TC:CF_VC))
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.addImm(0) // ADDR
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.addImm(AluInstCount - 1); // COUNT
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return ClauseFile(MIb, ClauseContent);
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}
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void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const {
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static const unsigned LiteralRegs[] = {
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AMDGPU::ALU_LITERAL_X,
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AMDGPU::ALU_LITERAL_Y,
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AMDGPU::ALU_LITERAL_Z,
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AMDGPU::ALU_LITERAL_W
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};
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3 > Srcs =
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TII->getSrcs(MI);
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for (unsigned i = 0, e = Srcs.size(); i < e; ++i) {
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if (Srcs[i].first->getReg() != AMDGPU::ALU_LITERAL_X)
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continue;
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int64_t Imm = Srcs[i].second;
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std::vector<int64_t>::iterator It =
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std::find(Lits.begin(), Lits.end(), Imm);
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if (It != Lits.end()) {
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unsigned Index = It - Lits.begin();
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Srcs[i].first->setReg(LiteralRegs[Index]);
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} else {
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assert(Lits.size() < 4 && "Too many literals in Instruction Group");
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Srcs[i].first->setReg(LiteralRegs[Lits.size()]);
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Lits.push_back(Imm);
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}
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}
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}
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MachineBasicBlock::iterator insertLiterals(
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MachineBasicBlock::iterator InsertPos,
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const std::vector<unsigned> &Literals) const {
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MachineBasicBlock *MBB = InsertPos->getParent();
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for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
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unsigned LiteralPair0 = Literals[i];
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unsigned LiteralPair1 = (i + 1 < e)?Literals[i + 1]:0;
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InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
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TII->get(AMDGPU::LITERALS))
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.addImm(LiteralPair0)
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.addImm(LiteralPair1);
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}
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return InsertPos;
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}
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ClauseFile
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MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
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const {
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MachineBasicBlock::iterator ClauseHead = I;
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std::vector<MachineInstr *> ClauseContent;
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I++;
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for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) {
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if (IsTrivialInst(I)) {
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++I;
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continue;
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}
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if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
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break;
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std::vector<int64_t> Literals;
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if (I->isBundle()) {
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MachineInstr *DeleteMI = I;
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MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
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while (++BI != E && BI->isBundledWithPred()) {
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BI->unbundleFromPred();
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for (unsigned i = 0, e = BI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = BI->getOperand(i);
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if (MO.isReg() && MO.isInternalRead())
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MO.setIsInternalRead(false);
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}
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getLiteral(BI, Literals);
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ClauseContent.push_back(BI);
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}
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I = BI;
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DeleteMI->eraseFromParent();
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} else {
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getLiteral(I, Literals);
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ClauseContent.push_back(I);
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I++;
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}
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for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
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unsigned literal0 = Literals[i];
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unsigned literal2 = (i + 1 < e)?Literals[i + 1]:0;
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MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
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TII->get(AMDGPU::LITERALS))
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.addImm(literal0)
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.addImm(literal2);
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ClauseContent.push_back(MILit);
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}
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}
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assert(ClauseContent.size() < 128 && "ALU clause is too big");
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ClauseHead->getOperand(7).setImm(ClauseContent.size() - 1);
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return ClauseFile(ClauseHead, ClauseContent);
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}
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void
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EmitFetchClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
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unsigned &CfCount) {
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CounterPropagateAddr(Clause.first, CfCount);
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MachineBasicBlock *BB = Clause.first->getParent();
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BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::FETCH_CLAUSE))
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.addImm(CfCount);
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for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
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BB->splice(InsertPos, BB, Clause.second[i]);
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}
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CfCount += 2 * Clause.second.size();
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}
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void
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EmitALUClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
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unsigned &CfCount) {
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Clause.first->getOperand(0).setImm(0);
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CounterPropagateAddr(Clause.first, CfCount);
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MachineBasicBlock *BB = Clause.first->getParent();
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BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::ALU_CLAUSE))
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.addImm(CfCount);
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for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
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BB->splice(InsertPos, BB, Clause.second[i]);
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}
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CfCount += Clause.second.size();
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}
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void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
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MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm());
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}
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void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
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const {
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for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
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It != E; ++It) {
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MachineInstr *MI = *It;
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CounterPropagateAddr(MI, Addr);
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}
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}
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unsigned getHWStackSize(unsigned StackSubEntry, bool hasPush) const {
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switch (ST.getGeneration()) {
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case AMDGPUSubtarget::R600:
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case AMDGPUSubtarget::R700:
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if (hasPush)
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StackSubEntry += 2;
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break;
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case AMDGPUSubtarget::EVERGREEN:
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if (hasPush)
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StackSubEntry ++;
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case AMDGPUSubtarget::NORTHERN_ISLANDS:
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StackSubEntry += 2;
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break;
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default: llvm_unreachable("Not a VLIW4/VLIW5 GPU");
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}
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return (StackSubEntry + 3)/4; // Need ceil value of StackSubEntry/4
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}
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public:
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R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
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TII (0), TRI(0),
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ST(tm.getSubtarget<AMDGPUSubtarget>()) {
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const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
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MaxFetchInst = ST.getTexVTXClauseSize();
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
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TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
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unsigned MaxStack = 0;
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unsigned CurrentStack = 0;
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bool HasPush = false;
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for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
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++MB) {
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MachineBasicBlock &MBB = *MB;
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unsigned CfCount = 0;
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std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
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std::vector<MachineInstr * > IfThenElseStack;
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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if (MFI->ShaderType == 1) {
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BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
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getHWInstrDesc(CF_CALL_FS));
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CfCount++;
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MaxStack = 1;
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}
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std::vector<ClauseFile> FetchClauses, AluClauses;
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std::vector<MachineInstr *> LastAlu(1);
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std::vector<MachineInstr *> ToPopAfter;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E;) {
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if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
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DEBUG(dbgs() << CfCount << ":"; I->dump(););
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FetchClauses.push_back(MakeFetchClause(MBB, I));
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CfCount++;
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continue;
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}
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MachineBasicBlock::iterator MI = I;
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if (MI->getOpcode() != AMDGPU::ENDIF)
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LastAlu.back() = 0;
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if (MI->getOpcode() == AMDGPU::CF_ALU)
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LastAlu.back() = MI;
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I++;
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switch (MI->getOpcode()) {
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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CurrentStack++;
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MaxStack = std::max(MaxStack, CurrentStack);
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HasPush = true;
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case AMDGPU::CF_ALU:
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I = MI;
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AluClauses.push_back(MakeALUClause(MBB, I));
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case AMDGPU::EG_ExportBuf:
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case AMDGPU::EG_ExportSwz:
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case AMDGPU::R600_ExportBuf:
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case AMDGPU::R600_ExportSwz:
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case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
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case AMDGPU::RAT_STORE_DWORD_cm:
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DEBUG(dbgs() << CfCount << ":"; MI->dump(););
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CfCount++;
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break;
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case AMDGPU::WHILELOOP: {
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CurrentStack+=4;
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MaxStack = std::max(MaxStack, CurrentStack);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_WHILE_LOOP))
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.addImm(1);
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std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
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std::set<MachineInstr *>());
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Pair.second.insert(MIb);
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LoopStack.push_back(Pair);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ENDLOOP: {
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CurrentStack-=4;
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std::pair<unsigned, std::set<MachineInstr *> > Pair =
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LoopStack.back();
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LoopStack.pop_back();
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CounterPropagateAddr(Pair.second, CfCount);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END_LOOP))
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.addImm(Pair.first + 1);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::IF_PREDICATE_SET: {
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LastAlu.push_back(0);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_JUMP))
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.addImm(0)
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.addImm(0);
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IfThenElseStack.push_back(MIb);
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DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ELSE: {
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MachineInstr * JumpInst = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(JumpInst, CfCount);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_ELSE))
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.addImm(0)
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.addImm(0);
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DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
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IfThenElseStack.push_back(MIb);
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MI->eraseFromParent();
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CfCount++;
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break;
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}
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case AMDGPU::ENDIF: {
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CurrentStack--;
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if (LastAlu.back()) {
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ToPopAfter.push_back(LastAlu.back());
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} else {
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_POP))
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.addImm(CfCount + 1)
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.addImm(1);
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(void)MIb;
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DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
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CfCount++;
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}
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MachineInstr *IfOrElseInst = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(IfOrElseInst, CfCount);
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IfOrElseInst->getOperand(1).setImm(1);
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LastAlu.pop_back();
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::PREDICATED_BREAK: {
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CurrentStack--;
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CfCount += 3;
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_JUMP))
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.addImm(CfCount)
|
|
.addImm(1);
|
|
MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
|
|
getHWInstrDesc(CF_LOOP_BREAK))
|
|
.addImm(0);
|
|
BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_POP))
|
|
.addImm(CfCount)
|
|
.addImm(1);
|
|
LoopStack.back().second.insert(MIb);
|
|
MI->eraseFromParent();
|
|
break;
|
|
}
|
|
case AMDGPU::CONTINUE: {
|
|
MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
|
|
getHWInstrDesc(CF_LOOP_CONTINUE))
|
|
.addImm(0);
|
|
LoopStack.back().second.insert(MIb);
|
|
MI->eraseFromParent();
|
|
CfCount++;
|
|
break;
|
|
}
|
|
case AMDGPU::RETURN: {
|
|
BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END));
|
|
CfCount++;
|
|
MI->eraseFromParent();
|
|
if (CfCount % 2) {
|
|
BuildMI(MBB, I, MBB.findDebugLoc(MI), TII->get(AMDGPU::PAD));
|
|
CfCount++;
|
|
}
|
|
for (unsigned i = 0, e = FetchClauses.size(); i < e; i++)
|
|
EmitFetchClause(I, FetchClauses[i], CfCount);
|
|
for (unsigned i = 0, e = AluClauses.size(); i < e; i++)
|
|
EmitALUClause(I, AluClauses[i], CfCount);
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
for (unsigned i = 0, e = ToPopAfter.size(); i < e; ++i) {
|
|
MachineInstr *Alu = ToPopAfter[i];
|
|
BuildMI(MBB, Alu, MBB.findDebugLoc((MachineBasicBlock::iterator)Alu),
|
|
TII->get(AMDGPU::CF_ALU_POP_AFTER))
|
|
.addImm(Alu->getOperand(0).getImm())
|
|
.addImm(Alu->getOperand(1).getImm())
|
|
.addImm(Alu->getOperand(2).getImm())
|
|
.addImm(Alu->getOperand(3).getImm())
|
|
.addImm(Alu->getOperand(4).getImm())
|
|
.addImm(Alu->getOperand(5).getImm())
|
|
.addImm(Alu->getOperand(6).getImm())
|
|
.addImm(Alu->getOperand(7).getImm())
|
|
.addImm(Alu->getOperand(8).getImm());
|
|
Alu->eraseFromParent();
|
|
}
|
|
MFI->StackSize = getHWStackSize(MaxStack, HasPush);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
const char *getPassName() const {
|
|
return "R600 Control Flow Finalizer Pass";
|
|
}
|
|
};
|
|
|
|
char R600ControlFlowFinalizer::ID = 0;
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
|
|
return new R600ControlFlowFinalizer(TM);
|
|
}
|