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https://github.com/RPCS3/llvm.git
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5c10a029ad
need to be updated for the new vector shuffle lowering. After talking to Adam Nemet, Tim Northover, etc., it seems that testing MC encodings in the same suite as the basic codegen isn't the right approach. Instead, we're going to want dedicated MC tests for the encodings. These encodings are starting to get in my way so I wanted to cut them out early. The total set of instructions that should have encoding tests added is: vpaddd vsqrtss vsqrtsd vmovlhps vmovhlps valignq vbroadcastss Not too many parts of these tests were even using this. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218932 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
14 KiB
LLVM
363 lines
14 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK: LCP
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; CHECK: .long 2
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 0
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK: .long 0
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 4
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK-LABEL: test1:
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; CHECK: vpermps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %a) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x float> %c
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}
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; CHECK-LABEL: test2:
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; CHECK: vpermd
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; CHECK: ret
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define <16 x i32> @test2(<16 x i32> %a) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x i32> %c
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}
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; CHECK-LABEL: test3:
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; CHECK: vpermq
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; CHECK: ret
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define <8 x i64> @test3(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1>
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ret <8 x i64> %c
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}
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; CHECK-LABEL: test4:
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; CHECK: vpermpd
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; CHECK: ret
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define <8 x double> @test4(<8 x double> %a) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test5:
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; CHECK: vpermt2pd
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; CHECK: ret
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define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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ret <8 x double> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test5m:
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; CHECK: vpermt2pd {{.* {%k[1-7]} {z}}}
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define <8 x double> @test5m(<8 x double> %a, <8 x double> %b, i8 %mask) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x double> %c, <8 x double> zeroinitializer
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ret <8 x double> %res
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}
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; CHECK-LABEL: test6:
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; CHECK: vpermq $30
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; CHECK: ret
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define <8 x i64> @test6(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4>
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ret <8 x i64> %c
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}
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; CHECK-LABEL: test7:
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; CHECK: vpermt2q
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; CHECK: ret
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define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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ret <8 x i64> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test7m:
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; CHECK: vpermt2q {{.* {%k[1-7]} {z}}}
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define <8 x i64> @test7m(<8 x i64> %a, <8 x i64> %b, i8 %mask) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
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ret <8 x i64> %res
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}
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; The mem variant of vpermt2 with a writemask
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; CHECK-LABEL: test7mm:
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; CHECK: vpermt2q {{\(.*\).* {%k[1-7]} {z}}}
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define <8 x i64> @test7mm(<8 x i64> %a, <8 x i64> *%pb, i8 %mask) nounwind {
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%b = load <8 x i64>* %pb
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
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ret <8 x i64> %res
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}
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; CHECK-LABEL: test8:
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; CHECK: vpermt2d
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; CHECK: ret
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define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x i32> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test8m:
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; CHECK: vpermt2d {{.* {%k[1-7]} {z}}}
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define <16 x i32> @test8m(<16 x i32> %a, <16 x i32> %b, i16 %mask) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x i32> %c, <16 x i32> zeroinitializer
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ret <16 x i32> %res
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}
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; The mem variant of vpermt2 with a writemask
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; CHECK-LABEL: test8mm:
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; CHECK: vpermt2d {{\(.*\).* {%k[1-7]} {z}}}
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define <16 x i32> @test8mm(<16 x i32> %a, <16 x i32> *%pb, i16 %mask) nounwind {
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%b = load <16 x i32> * %pb
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x i32> %c, <16 x i32> zeroinitializer
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ret <16 x i32> %res
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}
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; CHECK-LABEL: test9:
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; CHECK: vpermt2ps
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; CHECK: ret
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define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x float> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test9m:
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; CHECK: vpermt2ps {{.*}} {%k{{.}}} {z}
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define <16 x float> @test9m(<16 x float> %a, <16 x float> %b, i16 %mask) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x float> %c, <16 x float> zeroinitializer
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ret <16 x float> %res
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}
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; CHECK-LABEL: test10:
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; CHECK: vpermt2ps (
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; CHECK: ret
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define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind {
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%c = load <16 x float>* %b
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%d = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x float> %d
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}
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; CHECK-LABEL: test11:
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; CHECK: vpermt2d
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; CHECK: ret
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define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind {
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%c = load <16 x i32>* %b
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%d = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x i32> %d
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}
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; CHECK-LABEL: test12
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; CHECK: vmovlhps {{.*}}
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; CHECK: ret
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define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) nounwind {
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%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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ret <4 x i32> %c
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}
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; CHECK-LABEL: test13
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; CHECK: vpermilps $-79, %zmm
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; CHECK: ret
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define <16 x float> @test13(<16 x float> %a) {
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%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x float> %b
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}
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; CHECK-LABEL: test14
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; CHECK: vpermilpd $-53, %zmm
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; CHECK: ret
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define <8 x double> @test14(<8 x double> %a) {
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%b = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32><i32 1, i32 1, i32 2, i32 3, i32 4, i32 4, i32 7, i32 7>
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ret <8 x double> %b
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}
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; CHECK-LABEL: test15
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; CHECK: vpshufd $-79, %zmm
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; CHECK: ret
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define <16 x i32> @test15(<16 x i32> %a) {
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%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: valign_test_v16f32
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; CHECK: valignd $2, %zmm0, %zmm0
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; CHECK: ret
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define <16 x float> @valign_test_v16f32(<16 x float> %a, <16 x float> %b) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
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ret <16 x float> %c
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}
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; CHECK-LABEL: valign_test_v16i32
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; CHECK: valignd $2, %zmm0, %zmm0
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; CHECK: ret
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define <16 x i32> @valign_test_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
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ret <16 x i32> %c
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}
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; CHECK-LABEL: test16
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; CHECK: valignq $2, %zmm0, %zmm1
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; CHECK: ret
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define <8 x double> @test16(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test16k
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; CHECK: valignq $2, %zmm0, %zmm1, %zmm2 {%k1}
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define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> %src
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ret <8 x i64> %res
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}
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; CHECK-LABEL: test16kz
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; CHECK: valignq $2, %zmm0, %zmm1, %zmm0 {%k1} {z}
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define <8 x i64> @test16kz(<8 x i64> %a, <8 x i64> %b, i8 %mask) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
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ret <8 x i64> %res
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}
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; CHECK-LABEL: test17
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; CHECK: vshufpd $19, %zmm1, %zmm0
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; CHECK: ret
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define <8 x double> @test17(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 9, i32 2, i32 10, i32 5, i32 undef, i32 undef, i32 undef>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test18
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; CHECK: vpunpckhdq %zmm
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; CHECK: ret
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define <16 x i32> @test18(<16 x i32> %a, <16 x i32> %c) {
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%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 2, i32 18, i32 3, i32 19,
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i32 6, i32 22, i32 7, i32 23,
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i32 10, i32 26, i32 11, i32 27,
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i32 14, i32 30, i32 15, i32 31>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: test19
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; CHECK: vpunpckldq %zmm
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; CHECK: ret
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define <16 x i32> @test19(<16 x i32> %a, <16 x i32> %c) {
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%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17,
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i32 4, i32 20, i32 5, i32 21,
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i32 8, i32 24, i32 9, i32 25,
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i32 12, i32 28, i32 13, i32 29>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: test20
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; CHECK: vpunpckhqdq %zmm
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; CHECK: ret
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define <8 x i64> @test20(<8 x i64> %a, <8 x i64> %c) {
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%b = shufflevector <8 x i64> %a, <8 x i64> %c, <8 x i32><i32 1, i32 9,
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i32 3, i32 11,
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i32 5, i32 13,
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i32 7, i32 15>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: test21
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; CHECK: vunpcklps %zmm
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; CHECK: ret
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define <16 x float> @test21(<16 x float> %a, <16 x float> %c) {
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%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17,
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i32 4, i32 20, i32 5, i32 21,
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i32 8, i32 24, i32 9, i32 25,
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i32 12, i32 28, i32 13, i32 29>
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ret <16 x float> %b
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}
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; CHECK-LABEL: test22
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; CHECK: vmovhlps {{.*}}
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; CHECK: ret
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define <4 x i32> @test22(<4 x i32> %a, <4 x i32> %b) nounwind {
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%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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ret <4 x i32> %c
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}
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; CHECK-LABEL: @test23
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; CHECK: vshufps $-112, %zmm
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; CHECK: ret
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define <16 x float> @test23(<16 x float> %a, <16 x float> %c) {
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%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 0, i32 17, i32 18, i32 4, i32 4, i32 21, i32 22, i32 8, i32 8, i32 25, i32 26, i32 12, i32 12, i32 29, i32 30>
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ret <16 x float> %b
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}
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; CHECK-LABEL: @test24
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; CHECK: vpermt2d
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; CHECK: ret
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define <16 x i32> @test24(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <16 x i32> %c
|
|
}
|
|
|
|
; CHECK-LABEL: @test25
|
|
; CHECK: vshufps $52
|
|
; CHECK: ret
|
|
define <16 x i32> @test25(<16 x i32> %a, <16 x i32> %b) nounwind {
|
|
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 19, i32 undef, i32 4, i32 5, i32 23, i32 undef, i32 8, i32 9, i32 27, i32 undef, i32 12, i32 13, i32 undef, i32 undef>
|
|
ret <16 x i32> %c
|
|
}
|
|
|
|
; CHECK-LABEL: @test26
|
|
; CHECK: vmovshdup
|
|
; CHECK: ret
|
|
define <16 x i32> @test26(<16 x i32> %a) nounwind {
|
|
%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 undef, i32 9, i32 9, i32 undef, i32 11, i32 13, i32 undef, i32 undef, i32 undef>
|
|
ret <16 x i32> %c
|
|
}
|
|
|
|
; CHECK-LABEL: @test27
|
|
; CHECK: ret
|
|
define <16 x i32> @test27(<4 x i32>%a) {
|
|
%res = shufflevector <4 x i32> %a, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
ret <16 x i32> %res
|
|
}
|
|
|
|
; CHECK-LABEL: @test28
|
|
; CHECK: vinserti64x4 $1
|
|
; CHECK: ret
|
|
define <16 x i32> @test28(<16 x i32>%x, <16 x i32>%y) {
|
|
%res = shufflevector <16 x i32>%x, <16 x i32>%y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
|
|
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
|
|
ret <16 x i32> %res
|
|
}
|
|
|
|
; CHECK-LABEL: @test29
|
|
; CHECK: vinserti64x4 $0
|
|
; CHECK: ret
|
|
define <16 x i32> @test29(<16 x i32>%x, <16 x i32>%y) {
|
|
%res = shufflevector <16 x i32>%x, <16 x i32>%y, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
|
|
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
|
ret <16 x i32> %res
|
|
}
|
|
|