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760a46522a
The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172 91177308-0d34-0410-b5e6-96231b3b80d8
256 lines
9.2 KiB
C++
256 lines
9.2 KiB
C++
//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the ARM Calling Convention that
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// aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
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#define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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// APCS f64 is in register pairs, possibly split to stack
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static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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CCState &State, bool CanFail) {
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static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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// Try to get the first register.
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if (unsigned Reg = State.AllocateReg(RegList, 4))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else {
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// For the 2nd half of a v2f64, do not fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(8, 4),
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LocVT, LocInfo));
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return true;
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}
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// Try to get the second register.
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if (unsigned Reg = State.AllocateReg(RegList, 4))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(4, 4),
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LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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// AAPCS f64 is in aligned register pairs
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static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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CCState &State, bool CanFail) {
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static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
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static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
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if (Reg == 0) {
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// If we had R3 unallocated only, now we still must to waste it.
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Reg = State.AllocateReg(GPRArgRegs, 4);
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assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
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// For the 2nd half of a v2f64, do not just fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(8, 8),
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LocVT, LocInfo));
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return true;
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}
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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unsigned T = State.AllocateReg(LoRegList[i]);
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(void)T;
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assert(T == LoRegList[i] && "Could not allocate register");
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo, CCState &State) {
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static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
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if (Reg == 0)
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return false; // we didn't handle it
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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return true; // we handled it
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}
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static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
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State);
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}
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static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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ARM::S4, ARM::S5, ARM::S6, ARM::S7,
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ARM::S8, ARM::S9, ARM::S10, ARM::S11,
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ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
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static const uint16_t DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
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// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
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// has InConsecutiveRegs set, and that the last member also has
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// InConsecutiveRegsLast set. We must process all members of the HA before
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// we can allocate it, as we need to know the total number of registers that
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// will be needed in order to (attempt to) allocate a contiguous block.
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static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs();
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// AAPCS HFAs must have 1-4 elements, all of the same type
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assert(PendingHAMembers.size() < 4);
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if (PendingHAMembers.size() > 0)
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assert(PendingHAMembers[0].getLocVT() == LocVT);
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// Add the argument to the list to be allocated once we know the size of the
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// HA
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PendingHAMembers.push_back(
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CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
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if (ArgFlags.isInConsecutiveRegsLast()) {
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assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 &&
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"Homogeneous aggregates must have between 1 and 4 members");
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// Try to allocate a contiguous block of registers, each of the correct
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// size to hold one member.
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const uint16_t *RegList;
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unsigned NumRegs;
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switch (LocVT.SimpleTy) {
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case MVT::f32:
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RegList = SRegList;
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NumRegs = 16;
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break;
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case MVT::f64:
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RegList = DRegList;
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NumRegs = 8;
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break;
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case MVT::v2f64:
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RegList = QRegList;
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NumRegs = 4;
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break;
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default:
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llvm_unreachable("Unexpected member type for HA");
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break;
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}
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unsigned RegResult =
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State.AllocateRegBlock(RegList, NumRegs, PendingHAMembers.size());
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if (RegResult) {
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for (SmallVectorImpl<CCValAssign>::iterator It = PendingHAMembers.begin();
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It != PendingHAMembers.end(); ++It) {
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It->convertToReg(RegResult);
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State.addLoc(*It);
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++RegResult;
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}
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PendingHAMembers.clear();
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return true;
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}
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// Register allocation failed, fall back to the stack
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// Mark all VFP regs as unavailable (AAPCS rule C.2.vfp)
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for (unsigned regNo = 0; regNo < 16; ++regNo)
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State.AllocateReg(SRegList[regNo]);
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unsigned Size = LocVT.getSizeInBits() / 8;
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unsigned Align = std::min(Size, 8U);
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for (auto It : PendingHAMembers) {
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It.convertToMem(State.AllocateStack(Size, Align));
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State.addLoc(It);
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}
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// All pending members have now been allocated
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PendingHAMembers.clear();
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}
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// This will be allocated by the last member of the HA
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return true;
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}
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} // End llvm namespace
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#endif
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