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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
395 lines
13 KiB
C++
395 lines
13 KiB
C++
//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM addressing mode implementation stuff.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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namespace llvm {
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/// ARM_AM - ARM Addressing Mode Stuff
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namespace ARM_AM {
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enum ShiftOpc {
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no_shift = 0,
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asr,
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lsl,
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lsr,
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ror,
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rrx
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};
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enum AddrOpc {
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add = '+', sub = '-'
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};
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static inline const char *getShiftOpcStr(ShiftOpc Op) {
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switch (Op) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr: return "asr";
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case ARM_AM::lsl: return "lsl";
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case ARM_AM::lsr: return "lsr";
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case ARM_AM::ror: return "ror";
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case ARM_AM::rrx: return "rrx";
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}
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}
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static inline ShiftOpc getShiftOpcForNode(SDOperand N) {
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switch (N.getOpcode()) {
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default: return ARM_AM::no_shift;
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case ISD::SHL: return ARM_AM::lsl;
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case ISD::SRL: return ARM_AM::lsr;
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case ISD::SRA: return ARM_AM::asr;
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case ISD::ROTR: return ARM_AM::ror;
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//case ISD::ROTL: // Only if imm -> turn into ROTR.
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// Can't handle RRX here, because it would require folding a flag into
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// the addressing mode. :( This causes us to miss certain things.
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//case ARMISD::RRX: return ARM_AM::rrx;
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}
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}
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enum AMSubMode {
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bad_am_submode = 0,
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ia,
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ib,
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da,
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db
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};
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static inline const char *getAMSubModeStr(AMSubMode Mode) {
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switch (Mode) {
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default: assert(0 && "Unknown addressing sub-mode!");
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case ARM_AM::ia: return "ia";
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case ARM_AM::ib: return "ib";
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case ARM_AM::da: return "da";
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case ARM_AM::db: return "db";
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}
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}
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static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
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switch (Mode) {
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default: assert(0 && "Unknown addressing sub-mode!");
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case ARM_AM::ia: return isLD ? "fd" : "ea";
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case ARM_AM::ib: return isLD ? "ed" : "fa";
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case ARM_AM::da: return isLD ? "fa" : "ed";
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case ARM_AM::db: return isLD ? "ea" : "fd";
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}
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}
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/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
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///
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static inline unsigned rotr32(unsigned Val, unsigned Amt) {
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assert(Amt < 32 && "Invalid rotate amount");
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return (Val >> Amt) | (Val << ((32-Amt)&31));
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}
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/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
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///
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static inline unsigned rotl32(unsigned Val, unsigned Amt) {
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assert(Amt < 32 && "Invalid rotate amount");
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return (Val << Amt) | (Val >> ((32-Amt)&31));
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #1: shift_operand with registers
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//===--------------------------------------------------------------------===//
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//
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// This 'addressing mode' is used for arithmetic instructions. It can
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// represent things like:
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// reg
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// reg [asr|lsl|lsr|ror|rrx] reg
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// reg [asr|lsl|lsr|ror|rrx] imm
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//
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// This is stored three operands [rega, regb, opc]. The first is the base
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// reg, the second is the shift amount (or reg0 if not present or imm). The
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// third operand encodes the shift opcode and the imm if a reg isn't present.
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//
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static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
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return ShOp | (Imm << 3);
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}
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static inline unsigned getSORegOffset(unsigned Op) {
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return Op >> 3;
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}
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static inline ShiftOpc getSORegShOp(unsigned Op) {
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return (ShiftOpc)(Op & 7);
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}
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/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
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/// the 8-bit imm value.
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static inline unsigned getSOImmValImm(unsigned Imm) {
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return Imm & 0xFF;
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}
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/// getSOImmValRotate - Given an encoded imm field for the reg/imm form, return
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/// the rotate amount.
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static inline unsigned getSOImmValRot(unsigned Imm) {
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return (Imm >> 8) * 2;
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}
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/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
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/// computing the rotate amount to use. If this immediate value cannot be
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/// handled with a single shifter-op, determine a good rotate amount that will
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/// take a maximal chunk of bits out of the immediate.
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static inline unsigned getSOImmValRotate(unsigned Imm) {
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// 8-bit (or less) immediates are trivially shifter_operands with a rotate
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// of zero.
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if ((Imm & ~255U) == 0) return 0;
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// Use CTZ to compute the rotate amount.
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unsigned TZ = CountTrailingZeros_32(Imm);
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// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
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// not 9.
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unsigned RotAmt = TZ & ~1;
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// If we can handle this spread, return it.
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if ((rotr32(Imm, RotAmt) & ~255U) == 0)
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return (32-RotAmt)&31; // HW rotates right, not left.
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// For values like 0xF000000F, we should skip the first run of ones, then
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// retry the hunt.
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if (Imm & 1) {
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unsigned TrailingOnes = CountTrailingZeros_32(~Imm);
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if (TrailingOnes != 32) { // Avoid overflow on 0xFFFFFFFF
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// Restart the search for a high-order bit after the initial seconds of
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// ones.
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unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1));
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// Rotate amount must be even.
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unsigned RotAmt2 = TZ2 & ~1;
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// If this fits, use it.
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if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0)
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return (32-RotAmt2)&31; // HW rotates right, not left.
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}
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}
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// Otherwise, we have no way to cover this span of bits with a single
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// shifter_op immediate. Return a chunk of bits that will be useful to
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// handle.
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return (32-RotAmt)&31; // HW rotates right, not left.
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}
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/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
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/// into an shifter_operand immediate operand, return the 12-bit encoding for
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/// it. If not, return -1.
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static inline int getSOImmVal(unsigned Arg) {
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// 8-bit (or less) immediates are trivially shifter_operands with a rotate
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// of zero.
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if ((Arg & ~255U) == 0) return Arg;
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unsigned RotAmt = getSOImmValRotate(Arg);
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// If this cannot be handled with a single shifter_op, bail out.
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if (rotr32(~255U, RotAmt) & Arg)
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return -1;
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// Encode this correctly.
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return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
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}
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/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
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/// or'ing together two SOImmVal's.
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static inline bool isSOImmTwoPartVal(unsigned V) {
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// If this can be handled with a single shifter_op, bail out.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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if (V == 0)
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return false;
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// If this can be handled with two shifter_op's, accept.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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return V == 0;
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}
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/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
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/// return the first chunk of it.
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static inline unsigned getSOImmTwoPartFirst(unsigned V) {
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return rotr32(255U, getSOImmValRotate(V)) & V;
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}
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/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
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/// return the second chunk of it.
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static inline unsigned getSOImmTwoPartSecond(unsigned V) {
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// Mask out the first hunk.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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// Take what's left.
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assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
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return V;
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}
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/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
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/// by a left shift. Returns the shift amount to use.
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static inline unsigned getThumbImmValShift(unsigned Imm) {
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// 8-bit (or less) immediates are trivially immediate operand with a shift
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// of zero.
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if ((Imm & ~255U) == 0) return 0;
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// Use CTZ to compute the shift amount.
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return CountTrailingZeros_32(Imm);
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}
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/// isThumbImmShiftedVal - Return true if the specified value can be obtained
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/// by left shifting a 8-bit immediate.
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static inline bool isThumbImmShiftedVal(unsigned V) {
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// If this can be handled with
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V = (~255U << getThumbImmValShift(V)) & V;
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return V == 0;
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}
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/// getThumbImmNonShiftedVal - If V is a value that satisfies
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/// isThumbImmShiftedVal, return the non-shiftd value.
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static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
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return V >> getThumbImmValShift(V);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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//===--------------------------------------------------------------------===//
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//
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// This is used for most simple load/store instructions.
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//
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// addrmode2 := reg +/- reg shop imm
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// addrmode2 := reg +/- imm12
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//
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
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//
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// If this addressing mode is a frame index (before prolog/epilog insertion
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// and code rewriting), this operand will have the form: FI#, reg0, <offs>
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// with no shift amount for the frame offset.
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//
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static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
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assert(Imm12 < (1 << 12) && "Imm too large!");
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bool isSub = Opc == sub;
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return Imm12 | ((int)isSub << 12) | (SO << 13);
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}
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static inline unsigned getAM2Offset(unsigned AM2Opc) {
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return AM2Opc & ((1 << 12)-1);
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}
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static inline AddrOpc getAM2Op(unsigned AM2Opc) {
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return ((AM2Opc >> 12) & 1) ? sub : add;
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}
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static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
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return (ShiftOpc)(AM2Opc >> 13);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #3
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//===--------------------------------------------------------------------===//
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//
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// This is used for sign-extending loads, and load/store-pair instructions.
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//
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// addrmode3 := reg +/- reg
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// addrmode3 := reg +/- imm8
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//
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 8, the immediate in bits 0-7.
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/// getAM3Opc - This function encodes the addrmode3 opc field.
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static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
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bool isSub = Opc == sub;
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return ((int)isSub << 8) | Offset;
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}
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static inline unsigned char getAM3Offset(unsigned AM3Opc) {
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return AM3Opc & 0xFF;
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}
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static inline AddrOpc getAM3Op(unsigned AM3Opc) {
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return ((AM3Opc >> 8) & 1) ? sub : add;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #4
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//===--------------------------------------------------------------------===//
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//
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// This is used for load / store multiple instructions.
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//
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// addrmode4 := reg, <mode>
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//
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// The four modes are:
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// IA - Increment after
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// IB - Increment before
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// DA - Decrement after
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// DB - Decrement before
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//
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// If the 4th bit (writeback)is set, then the base register is updated after
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// the memory transfer.
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static inline AMSubMode getAM4SubMode(unsigned Mode) {
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return (AMSubMode)(Mode & 0x7);
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}
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static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) {
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return (int)SubMode | ((int)WB << 3);
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}
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static inline bool getAM4WBFlag(unsigned Mode) {
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return (Mode >> 3) & 1;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #5
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//===--------------------------------------------------------------------===//
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//
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// This is used for coprocessor instructions, such as FP load/stores.
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//
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// addrmode5 := reg +/- imm8*4
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//
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// The first operand is always a Reg. The third field encodes the operation
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// in bit 8, the immediate in bits 0-7.
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//
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// This can also be used for FP load/store multiple ops. The third field encodes
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// writeback mode in bit 8, the number of registers (or 2 times the number of
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// registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the
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// following two sub-modes:
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//
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// IA - Increment after
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// DB - Decrement before
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/// getAM5Opc - This function encodes the addrmode5 opc field.
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static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
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bool isSub = Opc == sub;
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return ((int)isSub << 8) | Offset;
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}
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static inline unsigned char getAM5Offset(unsigned AM5Opc) {
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return AM5Opc & 0xFF;
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}
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static inline AddrOpc getAM5Op(unsigned AM5Opc) {
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return ((AM5Opc >> 8) & 1) ? sub : add;
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}
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/// getAM5Opc - This function encodes the addrmode5 opc field for FLDM and
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/// FSTM instructions.
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static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
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unsigned char Offset) {
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assert((SubMode == ia || SubMode == db) &&
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"Illegal addressing mode 5 sub-mode!");
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return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
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}
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static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
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return (AMSubMode)((AM5Opc >> 9) & 0x7);
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}
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static inline bool getAM5WBFlag(unsigned AM5Opc) {
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return ((AM5Opc >> 8) & 1);
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}
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} // end namespace ARM_AM
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} // end namespace llvm
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#endif
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