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9724873c31
See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
941 B
ArmAsm
35 lines
941 B
ArmAsm
// RUN: not llvm-mc -arch arm -mattr=+v5te \
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// RUN: < %s >/dev/null 2> %t
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// RUN: grep "error: Rt must be even-numbered" %t | count 7
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// RUN: grep "error: Rt can't be R14" %t | count 7
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// RUN: grep "error: destination operands must be sequential" %t | count 7
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// RUN: grep "error: base register needs to be different from destination registers" %t | count 4
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// rdar://14479793
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ldrd r1, r2, [pc, #0]
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ldrd lr, pc, [pc, #0]
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ldrd r0, r3, [pc, #0]
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ldrd r1, r2, [r3, #4]
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ldrd lr, pc, [r3, #4]
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ldrd r0, r3, [r4, #4]
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ldrd r1, r2, [r3], #4
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ldrd lr, pc, [r3], #4
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ldrd r0, r3, [r4], #4
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ldrd r1, r2, [r3, #4]!
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ldrd lr, pc, [r3, #4]!
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ldrd r0, r3, [r4, #4]!
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ldrd r1, r2, [r3, -r4]!
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ldrd lr, pc, [r3, -r4]!
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ldrd r0, r3, [r4, -r5]!
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ldrd r1, r2, [r3, r4]
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ldrd lr, pc, [r3, r4]
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ldrd r0, r3, [r4, r5]
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ldrd r1, r2, [r3], r4
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ldrd lr, pc, [r3], r4
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ldrd r0, r3, [r4], r5
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ldrd r0, r1, [r0], #4
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ldrd r0, r1, [r1], #4
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ldrd r0, r1, [r0, #4]!
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ldrd r0, r1, [r1, #4]!
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