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26b0000166
are either unreduced or only test old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133228 91177308-0d34-0410-b5e6-96231b3b80d8
345 lines
7.7 KiB
LLVM
345 lines
7.7 KiB
LLVM
; RUN: llc < %s -march=cellspu > %t1.s
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; RUN: grep {shlh } %t1.s | count 10
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; RUN: grep {shlhi } %t1.s | count 3
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; RUN: grep {shl } %t1.s | count 11
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; RUN: grep {shli } %t1.s | count 3
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; RUN: grep {xshw } %t1.s | count 5
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; RUN: grep {and } %t1.s | count 14
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; RUN: grep {andi } %t1.s | count 2
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; RUN: grep {rotmi } %t1.s | count 2
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; RUN: grep {rotqmbyi } %t1.s | count 1
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; RUN: grep {rotqmbii } %t1.s | count 2
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; RUN: grep {rotqmby } %t1.s | count 1
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; RUN: grep {rotqmbi } %t1.s | count 2
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; RUN: grep {rotqbyi } %t1.s | count 1
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; RUN: grep {rotqbii } %t1.s | count 2
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; RUN: grep {rotqbybi } %t1.s | count 1
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; RUN: grep {sfi } %t1.s | count 6
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; RUN: cat %t1.s | FileCheck %s
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; Shift left i16 via register, note that the second operand to shl is promoted
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; to a 32-bit type:
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define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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define signext i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define signext i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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define zeroext i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define zeroext i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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; Shift left i16 with immediate:
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define i16 @shlhi_i16_1(i16 %arg1) {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i16 @shlhi_i16_2(i16 %arg1) {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define i16 @shlhi_i16_3(i16 %arg1) {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i16 @shlhi_i16_4(i16 %arg1) {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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define signext i16 @shlhi_i16_5(i16 signext %arg1) {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define signext i16 @shlhi_i16_6(i16 signext %arg1) {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define signext i16 @shlhi_i16_7(i16 signext %arg1) {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define signext i16 @shlhi_i16_8(i16 signext %arg1) {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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define zeroext i16 @shlhi_i16_9(i16 zeroext %arg1) {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define zeroext i16 @shlhi_i16_10(i16 zeroext %arg1) {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define zeroext i16 @shlhi_i16_11(i16 zeroext %arg1) {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define zeroext i16 @shlhi_i16_12(i16 zeroext %arg1) {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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; Shift left i32 via register, note that the second operand to shl is promoted
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; to a 32-bit type:
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define i32 @shl_i32_1(i32 %arg1, i32 %arg2) {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define i32 @shl_i32_2(i32 %arg1, i32 %arg2) {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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define signext i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define signext i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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define zeroext i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define zeroext i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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; Shift left i32 with immediate:
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define i32 @shli_i32_1(i32 %arg1) {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i32 @shli_i32_2(i32 %arg1) {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define i32 @shli_i32_3(i32 %arg1) {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i32 @shli_i32_4(i32 %arg1) {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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define signext i32 @shli_i32_5(i32 signext %arg1) {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define signext i32 @shli_i32_6(i32 signext %arg1) {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define signext i32 @shli_i32_7(i32 signext %arg1) {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define signext i32 @shli_i32_8(i32 signext %arg1) {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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define zeroext i32 @shli_i32_9(i32 zeroext %arg1) {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define zeroext i32 @shli_i32_10(i32 zeroext %arg1) {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define zeroext i32 @shli_i32_11(i32 zeroext %arg1) {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define zeroext i32 @shli_i32_12(i32 zeroext %arg1) {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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;; i64 shift left
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define i64 @shl_i64_1(i64 %arg1) {
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%A = shl i64 %arg1, 9
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ret i64 %A
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}
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define i64 @shl_i64_2(i64 %arg1) {
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%A = shl i64 %arg1, 3
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ret i64 %A
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}
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define i64 @shl_i64_3(i64 %arg1, i32 %shift) {
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%1 = zext i32 %shift to i64
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%2 = shl i64 %arg1, %1
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ret i64 %2
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}
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;; i64 shift right logical (shift 0s from the right)
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define i64 @lshr_i64_1(i64 %arg1) {
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%1 = lshr i64 %arg1, 9
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ret i64 %1
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}
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define i64 @lshr_i64_2(i64 %arg1) {
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%1 = lshr i64 %arg1, 3
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ret i64 %1
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}
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define i64 @lshr_i64_3(i64 %arg1, i32 %shift) {
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%1 = zext i32 %shift to i64
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%2 = lshr i64 %arg1, %1
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ret i64 %2
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}
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;; i64 shift right arithmetic (shift 1s from the right)
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define i64 @ashr_i64_1(i64 %arg) {
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%1 = ashr i64 %arg, 9
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ret i64 %1
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}
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define i64 @ashr_i64_2(i64 %arg) {
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%1 = ashr i64 %arg, 3
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ret i64 %1
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}
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define i64 @ashr_i64_3(i64 %arg1, i32 %shift) {
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%1 = zext i32 %shift to i64
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%2 = ashr i64 %arg1, %1
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ret i64 %2
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}
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define i32 @hi32_i64(i64 %arg) {
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%1 = lshr i64 %arg, 32
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%2 = trunc i64 %1 to i32
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ret i32 %2
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}
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; some random tests
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define i128 @test_lshr_i128( i128 %val ) {
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;CHECK: test_lshr_i128
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;CHECK: sfi
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;CHECK: rotqmbi
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;CHECK: rotqmbybi
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;CHECK: bi $lr
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%rv = lshr i128 %val, 64
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ret i128 %rv
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}
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;Vector shifts
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define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) {
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;CHECK: shl
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;CHECK: bi $lr
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%rv = shl <2 x i32> %val, %sh
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ret <2 x i32> %rv
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}
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define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: shl
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;CHECK: bi $lr
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%rv = shl <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: shlh
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;CHECK: bi $lr
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%rv = shl <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: rotm
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;CHECK: bi $lr
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%rv = lshr <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: sfhi
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;CHECK: rothm
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;CHECK: bi $lr
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%rv = lshr <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: rotma
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;CHECK: bi $lr
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%rv = ashr <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: sfhi
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;CHECK: rotmah
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;CHECK: bi $lr
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%rv = ashr <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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