llvm/lib/Target
Chris Lattner 98a8ba0393 Fix a problem where probing for addressing modes caused expressions to be
emitted too early.  In particular, this fixes
Regression/CodeGen/X86/regpressure.ll:regpressure3.

This also improves the 2nd basic block in 164.gzip:flush_block, which went from

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree + 20]
        movzx %ECX, WORD PTR [dyn_ltree + 16]
        mov DWORD PTR [%ESP + 32], %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        movzx %EDX, WORD PTR [dyn_ltree + 8]
        movzx %EBX, WORD PTR [dyn_ltree + 4]
        mov DWORD PTR [%ESP + 36], %EBX
        movzx %EBX, WORD PTR [dyn_ltree]
        add DWORD PTR [%ESP + 36], %EBX
        add %EDX, DWORD PTR [%ESP + 36]
        add %ECX, %EDX
        add DWORD PTR [%ESP + 32], %ECX
        add %EAX, DWORD PTR [%ESP + 32]
        movzx %ECX, WORD PTR [dyn_ltree + 24]
        add %EAX, %ECX
        mov %ECX, 0
        mov %EDX, %ECX

to

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree]
        movzx %ECX, WORD PTR [dyn_ltree + 4]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 8]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 16]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 20]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 24]
        add %ECX, %EAX
        mov %EAX, 0
        mov %EDX, %EAX

... which results in less spilling in the function.

This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc.  The
default isel takes 37.31s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19650 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-18 01:06:26 +00:00
..
CBackend Fix CBE code so that it compiles with VC++. 2005-01-06 04:21:49 +00:00
PowerPC Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll 2005-01-14 20:22:02 +00:00
Skeleton ignore generated files 2004-11-21 00:01:54 +00:00
Sparc Substantially improve the code generated by non-folded setcc instructions. 2005-01-01 16:06:57 +00:00
SparcV8 Substantially improve the code generated by non-folded setcc instructions. 2005-01-01 16:06:57 +00:00
SparcV9 Added tmp instructions to preserve ssa. 2005-01-17 06:47:26 +00:00
X86 Fix a problem where probing for addressing modes caused expressions to be 2005-01-18 01:06:26 +00:00
Makefile Add SparcV8 target back into the build 2004-12-10 04:54:21 +00:00
MRegisterInfo.cpp Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre. 2004-10-27 06:00:53 +00:00
Target.td Add some bits that can be set for instructions. 2005-01-02 02:27:48 +00:00
TargetData.cpp Initial support for packed types, contributed by Morten Ofstad 2004-12-01 17:14:28 +00:00
TargetFrameInfo.cpp Remove dead methods 2004-08-12 18:37:15 +00:00
TargetInstrInfo.cpp ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its 2004-07-27 21:43:38 +00:00
TargetMachine.cpp Add a new target-independent code generator flag. 2005-01-15 06:00:32 +00:00
TargetMachineRegistry.cpp Implement TargetRegistrationListener 2004-07-11 06:03:21 +00:00
TargetSchedInfo.cpp Improve compatiblity with HPUX on Itanium, patch by Duraid Madina 2005-01-16 01:31:31 +00:00