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c02a6fa7d8
In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133210 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.1 KiB
LLVM
25 lines
1.1 KiB
LLVM
; RUN: llc < %s
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;
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; This test would crash because isel creates a GPR register for the return
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; value from f1. The register is only used by tBLXr_r9 which accepts a full GPR
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; register, but we cannot have live GPRs in thumb mode because we don't know how
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; to spill them.
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;
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; <rdar://problem/9624323>
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
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target triple = "thumbv6-apple-darwin10"
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%0 = type opaque
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declare i8* (i8*, i8*, ...)* @f1(i8*, i8*) optsize
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declare i8* @f2(i8*, i8*, ...)
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define internal void @f(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize ssp {
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entry:
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%call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*)* @f1(i8* undef, i8* %_cmd) optsize
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%0 = bitcast i8* (i8*, i8*, ...)* %call14 to void (i8*, i8*, %0*, %0*)*
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tail call void %0(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize
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tail call void bitcast (i8* (i8*, i8*, ...)* @f2 to void (i8*, i8*, i32, %0*, %0*)*)(i8* %self, i8* undef, i32 2, %0* %inIndexes, %0* undef) optsize
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ret void
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}
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