Craig Topper 98e0aa0b32 [X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend. ...

This patch enables the use of lowerShuffleAsBitMask for 512-bit blends before
falling back to move immedate, GPR to k-register, and masked op.

I had to make some changes to support v8i64 when i64 is not a legal type. And to
support floating point types.

This trades a load for the move immediate and GPR move which is higher latency.
But its probably better for register pressure not having to hop through other
register classes. The load+and should play better with LICM and
rematerialization I think.

Differential Revision: https://reviews.llvm.org/D59479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356618 91177308-0d34-0410-b5e6-96231b3b80d8

2019-03-20 21:30:20 +00:00

..

AArch64

[AArch64][GlobalISel] Add an optimization to select vector DUP instructions.

2019-03-19 21:43:05 +00:00

AMDGPU

AMDGPU: Don't look for constant in insert/extract_vector_elt regbankselect

2019-03-20 20:41:34 +00:00

ARC

[ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores.

2019-03-20 20:06:21 +00:00

ARM

[ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.

2019-03-20 19:40:45 +00:00

AVR

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00

BPF

[BPF] Add BTF Var and DataSec Support

2019-03-16 15:36:31 +00:00

Generic

[AVR] Remove unneeded XFAILs from the Generic CodeGen tests

2019-01-20 11:16:58 +00:00

Hexagon

[Hexagon] Remove icmp undef from reduced tests

2019-03-15 15:07:44 +00:00

Inputs

…

Lanai

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

Mips

RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs

2019-03-19 19:01:34 +00:00

MIR

MIR: Allow targets to serialize MachineFunctionInfo

2019-03-14 22:54:43 +00:00

MSP430

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00

NVPTX

[Codegen] fix typos in test case

2019-03-02 08:03:59 +00:00

PowerPC

RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs

2019-03-19 19:01:34 +00:00

RISCV

[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs

2019-03-14 08:17:44 +00:00

SPARC

[SPARC] Regenerate label test for D59363

2019-03-15 11:24:17 +00:00

SystemZ

RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs

2019-03-19 19:01:34 +00:00

Thumb

[ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.

2019-03-20 19:40:45 +00:00

Thumb2

[ARM] Check that CPSR does not have other uses

2019-03-17 21:36:15 +00:00

WebAssembly

[WebAssembly] Target features section

2019-03-20 20:26:45 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

Fix invalid target triples in tests. (NFC)

2019-03-04 23:37:41 +00:00

X86

[X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend.

2019-03-20 21:30:20 +00:00

XCore

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13 17:07:09 +00:00