mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-19 09:57:42 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
483 lines
15 KiB
LLVM
483 lines
15 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
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%struct.uint8x16x2_t = type { [2 x <16 x i8>] }
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%struct.poly8x16x2_t = type { [2 x <16 x i8>] }
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%struct.uint8x16x3_t = type { [3 x <16 x i8>] }
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%struct.int8x16x2_t = type { [2 x <16 x i8>] }
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%struct.int16x8x2_t = type { [2 x <8 x i16>] }
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%struct.int32x4x2_t = type { [2 x <4 x i32>] }
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%struct.int64x2x2_t = type { [2 x <2 x i64>] }
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%struct.float32x4x2_t = type { [2 x <4 x float>] }
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%struct.float64x2x2_t = type { [2 x <2 x double>] }
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%struct.int8x8x2_t = type { [2 x <8 x i8>] }
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%struct.int16x4x2_t = type { [2 x <4 x i16>] }
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%struct.int32x2x2_t = type { [2 x <2 x i32>] }
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%struct.int64x1x2_t = type { [2 x <1 x i64>] }
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%struct.float32x2x2_t = type { [2 x <2 x float>] }
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%struct.float64x1x2_t = type { [2 x <1 x double>] }
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%struct.int8x16x3_t = type { [3 x <16 x i8>] }
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%struct.int16x8x3_t = type { [3 x <8 x i16>] }
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%struct.int32x4x3_t = type { [3 x <4 x i32>] }
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%struct.int64x2x3_t = type { [3 x <2 x i64>] }
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%struct.float32x4x3_t = type { [3 x <4 x float>] }
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%struct.float64x2x3_t = type { [3 x <2 x double>] }
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%struct.int8x8x3_t = type { [3 x <8 x i8>] }
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%struct.int16x4x3_t = type { [3 x <4 x i16>] }
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%struct.int32x2x3_t = type { [3 x <2 x i32>] }
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%struct.int64x1x3_t = type { [3 x <1 x i64>] }
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%struct.float32x2x3_t = type { [3 x <2 x float>] }
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%struct.float64x1x3_t = type { [3 x <1 x double>] }
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%struct.int8x16x4_t = type { [4 x <16 x i8>] }
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%struct.int16x8x4_t = type { [4 x <8 x i16>] }
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%struct.int32x4x4_t = type { [4 x <4 x i32>] }
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%struct.int64x2x4_t = type { [4 x <2 x i64>] }
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%struct.float32x4x4_t = type { [4 x <4 x float>] }
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%struct.float64x2x4_t = type { [4 x <2 x double>] }
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%struct.int8x8x4_t = type { [4 x <8 x i8>] }
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%struct.int16x4x4_t = type { [4 x <4 x i16>] }
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%struct.int32x2x4_t = type { [4 x <2 x i32>] }
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%struct.int64x1x4_t = type { [4 x <1 x i64>] }
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%struct.float32x2x4_t = type { [4 x <2 x float>] }
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%struct.float64x1x4_t = type { [4 x <1 x double>] }
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define <16 x i8> @test_ld_from_poll_v16i8(<16 x i8> %a) {
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; CHECK-LABEL: test_ld_from_poll_v16i8:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 2, i8 13, i8 14, i8 15, i8 16>
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ret <16 x i8> %b
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}
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define <8 x i16> @test_ld_from_poll_v8i16(<8 x i16> %a) {
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; CHECK-LABEL: test_ld_from_poll_v8i16:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <8 x i16> %a, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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ret <8 x i16> %b
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}
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define <4 x i32> @test_ld_from_poll_v4i32(<4 x i32> %a) {
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; CHECK-LABEL: test_ld_from_poll_v4i32:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <4 x i32> %a, <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i32> %b
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}
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define <2 x i64> @test_ld_from_poll_v2i64(<2 x i64> %a) {
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; CHECK-LABEL: test_ld_from_poll_v2i64:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <2 x i64> %a, <i64 1, i64 2>
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ret <2 x i64> %b
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}
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define <4 x float> @test_ld_from_poll_v4f32(<4 x float> %a) {
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; CHECK-LABEL: test_ld_from_poll_v4f32:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>
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ret <4 x float> %b
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}
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define <2 x double> @test_ld_from_poll_v2f64(<2 x double> %a) {
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; CHECK-LABEL: test_ld_from_poll_v2f64:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = fadd <2 x double> %a, <double 1.0, double 2.0>
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ret <2 x double> %b
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}
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define <8 x i8> @test_ld_from_poll_v8i8(<8 x i8> %a) {
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; CHECK-LABEL: test_ld_from_poll_v8i8:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <8 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
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ret <8 x i8> %b
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}
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define <4 x i16> @test_ld_from_poll_v4i16(<4 x i16> %a) {
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; CHECK-LABEL: test_ld_from_poll_v4i16:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <4 x i16> %a, <i16 1, i16 2, i16 3, i16 4>
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ret <4 x i16> %b
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}
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define <2 x i32> @test_ld_from_poll_v2i32(<2 x i32> %a) {
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; CHECK-LABEL: test_ld_from_poll_v2i32:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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entry:
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%b = add <2 x i32> %a, <i32 1, i32 2>
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ret <2 x i32> %b
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}
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define <16 x i8> @test_vld1q_dup_s8(i8* %a) {
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; CHECK-LABEL: test_vld1q_dup_s8:
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; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0]
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entry:
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%0 = load i8* %a, align 1
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%1 = insertelement <16 x i8> undef, i8 %0, i32 0
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%lane = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %lane
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}
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define <8 x i16> @test_vld1q_dup_s16(i16* %a) {
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; CHECK-LABEL: test_vld1q_dup_s16:
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; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0]
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entry:
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%0 = load i16* %a, align 2
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0
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%lane = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %lane
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}
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define <4 x i32> @test_vld1q_dup_s32(i32* %a) {
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; CHECK-LABEL: test_vld1q_dup_s32:
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; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
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entry:
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%0 = load i32* %a, align 4
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0
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%lane = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %lane
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}
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define <2 x i64> @test_vld1q_dup_s64(i64* %a) {
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; CHECK-LABEL: test_vld1q_dup_s64:
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; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
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entry:
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%0 = load i64* %a, align 8
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%1 = insertelement <2 x i64> undef, i64 %0, i32 0
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%lane = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %lane
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}
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define <4 x float> @test_vld1q_dup_f32(float* %a) {
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; CHECK-LABEL: test_vld1q_dup_f32:
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; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
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entry:
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%0 = load float* %a, align 4
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%1 = insertelement <4 x float> undef, float %0, i32 0
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%lane = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %lane
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}
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define <2 x double> @test_vld1q_dup_f64(double* %a) {
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; CHECK-LABEL: test_vld1q_dup_f64:
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; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
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entry:
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%0 = load double* %a, align 8
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%1 = insertelement <2 x double> undef, double %0, i32 0
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%lane = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> zeroinitializer
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ret <2 x double> %lane
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}
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define <8 x i8> @test_vld1_dup_s8(i8* %a) {
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; CHECK-LABEL: test_vld1_dup_s8:
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; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0]
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entry:
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%0 = load i8* %a, align 1
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%1 = insertelement <8 x i8> undef, i8 %0, i32 0
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%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
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ret <8 x i8> %lane
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}
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define <4 x i16> @test_vld1_dup_s16(i16* %a) {
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; CHECK-LABEL: test_vld1_dup_s16:
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; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0]
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entry:
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%0 = load i16* %a, align 2
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%1 = insertelement <4 x i16> undef, i16 %0, i32 0
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%lane = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> zeroinitializer
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ret <4 x i16> %lane
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}
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define <2 x i32> @test_vld1_dup_s32(i32* %a) {
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; CHECK-LABEL: test_vld1_dup_s32:
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; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
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entry:
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%0 = load i32* %a, align 4
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%1 = insertelement <2 x i32> undef, i32 %0, i32 0
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%lane = shufflevector <2 x i32> %1, <2 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %lane
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}
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define <1 x i64> @test_vld1_dup_s64(i64* %a) {
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; CHECK-LABEL: test_vld1_dup_s64:
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; CHECK: ldr {{d[0-9]+}}, [x0]
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entry:
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%0 = load i64* %a, align 8
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%1 = insertelement <1 x i64> undef, i64 %0, i32 0
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ret <1 x i64> %1
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}
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define <2 x float> @test_vld1_dup_f32(float* %a) {
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; CHECK-LABEL: test_vld1_dup_f32:
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; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
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entry:
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%0 = load float* %a, align 4
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%1 = insertelement <2 x float> undef, float %0, i32 0
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%lane = shufflevector <2 x float> %1, <2 x float> undef, <2 x i32> zeroinitializer
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ret <2 x float> %lane
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}
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define <1 x double> @test_vld1_dup_f64(double* %a) {
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; CHECK-LABEL: test_vld1_dup_f64:
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; CHECK: ldr {{d[0-9]+}}, [x0]
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entry:
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%0 = load double* %a, align 8
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%1 = insertelement <1 x double> undef, double %0, i32 0
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ret <1 x double> %1
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}
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define <1 x i64> @testDUP.v1i64(i64* %a, i64* %b) #0 {
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; As there is a store operation depending on %1, LD1R pattern can't be selected.
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; So LDR and FMOV should be emitted.
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; CHECK-LABEL: testDUP.v1i64:
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
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; CHECK-DAG: fmov {{d[0-9]+}}, {{x[0-9]+}}
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; CHECK-DAG: str {{x[0-9]+}}, [{{x[0-9]+}}]
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%1 = load i64* %a, align 8
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store i64 %1, i64* %b, align 8
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%vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0
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ret <1 x i64> %vecinit.i
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}
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define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 {
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; As there is a store operation depending on %1, LD1R pattern can't be selected.
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; So LDR and FMOV should be emitted.
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; CHECK-LABEL: testDUP.v1f64:
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}]
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; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}]
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%1 = load double* %a, align 8
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store double %1, double* %b, align 8
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%vecinit.i = insertelement <1 x double> undef, double %1, i32 0
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ret <1 x double> %vecinit.i
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}
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define <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vld1q_lane_s8:
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; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
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entry:
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%0 = load i8* %a, align 1
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%vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15
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ret <16 x i8> %vld1_lane
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}
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define <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) {
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; CHECK-LABEL: test_vld1q_lane_s16:
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; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
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entry:
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%0 = load i16* %a, align 2
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%vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7
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ret <8 x i16> %vld1_lane
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}
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define <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vld1q_lane_s32:
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; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
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entry:
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%0 = load i32* %a, align 4
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%vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3
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ret <4 x i32> %vld1_lane
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}
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define <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vld1q_lane_s64:
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; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
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entry:
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%0 = load i64* %a, align 8
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%vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1
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ret <2 x i64> %vld1_lane
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}
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define <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) {
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; CHECK-LABEL: test_vld1q_lane_f32:
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; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
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entry:
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%0 = load float* %a, align 4
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%vld1_lane = insertelement <4 x float> %b, float %0, i32 3
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ret <4 x float> %vld1_lane
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}
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define <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) {
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; CHECK-LABEL: test_vld1q_lane_f64:
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; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
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entry:
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%0 = load double* %a, align 8
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%vld1_lane = insertelement <2 x double> %b, double %0, i32 1
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ret <2 x double> %vld1_lane
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}
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define <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) {
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; CHECK-LABEL: test_vld1_lane_s8:
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; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
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entry:
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%0 = load i8* %a, align 1
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%vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7
|
|
ret <8 x i8> %vld1_lane
|
|
}
|
|
|
|
define <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) {
|
|
; CHECK-LABEL: test_vld1_lane_s16:
|
|
; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = load i16* %a, align 2
|
|
%vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3
|
|
ret <4 x i16> %vld1_lane
|
|
}
|
|
|
|
define <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) {
|
|
; CHECK-LABEL: test_vld1_lane_s32:
|
|
; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = load i32* %a, align 4
|
|
%vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1
|
|
ret <2 x i32> %vld1_lane
|
|
}
|
|
|
|
define <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) {
|
|
; CHECK-LABEL: test_vld1_lane_s64:
|
|
; CHECK: ldr {{d[0-9]+}}, [x0]
|
|
entry:
|
|
%0 = load i64* %a, align 8
|
|
%vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0
|
|
ret <1 x i64> %vld1_lane
|
|
}
|
|
|
|
define <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) {
|
|
; CHECK-LABEL: test_vld1_lane_f32:
|
|
; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = load float* %a, align 4
|
|
%vld1_lane = insertelement <2 x float> %b, float %0, i32 1
|
|
ret <2 x float> %vld1_lane
|
|
}
|
|
|
|
define <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) {
|
|
; CHECK-LABEL: test_vld1_lane_f64:
|
|
; CHECK: ldr {{d[0-9]+}}, [x0]
|
|
entry:
|
|
%0 = load double* %a, align 8
|
|
%vld1_lane = insertelement <1 x double> undef, double %0, i32 0
|
|
ret <1 x double> %vld1_lane
|
|
}
|
|
|
|
define void @test_vst1q_lane_s8(i8* %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_s8:
|
|
; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <16 x i8> %b, i32 15
|
|
store i8 %0, i8* %a, align 1
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1q_lane_s16(i16* %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_s16:
|
|
; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <8 x i16> %b, i32 7
|
|
store i16 %0, i16* %a, align 2
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1q_lane_s32(i32* %a, <4 x i32> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_s32:
|
|
; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <4 x i32> %b, i32 3
|
|
store i32 %0, i32* %a, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1q_lane_s64(i64* %a, <2 x i64> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_s64:
|
|
; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <2 x i64> %b, i32 1
|
|
store i64 %0, i64* %a, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1q_lane_f32(float* %a, <4 x float> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_f32:
|
|
; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <4 x float> %b, i32 3
|
|
store float %0, float* %a, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1q_lane_f64(double* %a, <2 x double> %b) {
|
|
; CHECK-LABEL: test_vst1q_lane_f64:
|
|
; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <2 x double> %b, i32 1
|
|
store double %0, double* %a, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_s8(i8* %a, <8 x i8> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_s8:
|
|
; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <8 x i8> %b, i32 7
|
|
store i8 %0, i8* %a, align 1
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_s16(i16* %a, <4 x i16> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_s16:
|
|
; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <4 x i16> %b, i32 3
|
|
store i16 %0, i16* %a, align 2
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_s32(i32* %a, <2 x i32> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_s32:
|
|
; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <2 x i32> %b, i32 1
|
|
store i32 %0, i32* %a, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_s64(i64* %a, <1 x i64> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_s64:
|
|
; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <1 x i64> %b, i32 0
|
|
store i64 %0, i64* %a, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_f32(float* %a, <2 x float> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_f32:
|
|
; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
|
|
entry:
|
|
%0 = extractelement <2 x float> %b, i32 1
|
|
store float %0, float* %a, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @test_vst1_lane_f64(double* %a, <1 x double> %b) {
|
|
; CHECK-LABEL: test_vst1_lane_f64:
|
|
; CHECK: str {{d[0-9]+}}, [x0]
|
|
entry:
|
|
%0 = extractelement <1 x double> %b, i32 0
|
|
store double %0, double* %a, align 8
|
|
ret void
|
|
}
|