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https://github.com/RPCS3/llvm.git
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7896c9f436
Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
709 lines
25 KiB
C++
709 lines
25 KiB
C++
//===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "t2-reduce-size"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
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STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
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static cl::opt<int> ReduceLimit("t2-reduce-limit",
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cl::init(-1), cl::Hidden);
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static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
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cl::init(-1), cl::Hidden);
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static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
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cl::init(-1), cl::Hidden);
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namespace {
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/// ReduceTable - A static table with information on mapping from wide
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/// opcodes to narrow
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struct ReduceEntry {
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unsigned WideOpc; // Wide opcode
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unsigned NarrowOpc1; // Narrow opcode to transform to
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unsigned NarrowOpc2; // Narrow opcode when it's two-address
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uint8_t Imm1Limit; // Limit of immediate field (bits)
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uint8_t Imm2Limit; // Limit of immediate field when it's two-address
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unsigned LowRegs1 : 1; // Only possible if low-registers are used
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unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
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unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
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// 1 - No cc field.
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// 2 - Always set CPSR.
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unsigned PredCC2 : 2;
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unsigned Special : 1; // Needs to be dealt with specially
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};
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static const ReduceEntry ReduceTable[] = {
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// Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
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{ ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
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// Note: immediate scale is 4.
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{ ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
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{ ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
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{ ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0 },
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{ ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
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{ ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 0 },
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{ ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
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// FIXME: adr.n immediate offset must be multiple of 4.
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//{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
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{ ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1 },
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// FIXME: Do we need the 16-bit 'S' variant?
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{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
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{ ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 0, 0,1, 0 },
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{ ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 },
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{ ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 },
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{ ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 },
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{ ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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// FIXME: Clean this up after splitting each Thumb load / store opcode
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// into multiple ones.
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{ ARM::t2LDRi12,ARM::tLDR, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
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{ ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRBi12,ARM::tLDRB, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRHi12,ARM::tLDRH, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRi12,ARM::tSTR, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
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{ ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHi12,ARM::tSTRH, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDM_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 },
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{ ARM::t2LDM, ARM::tLDM, ARM::tPOP, 0, 0, 1, 1, 1,1, 1 },
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{ ARM::t2STM, ARM::tSTM, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 },
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};
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class Thumb2SizeReduce : public MachineFunctionPass {
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public:
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static char ID;
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Thumb2SizeReduce();
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const Thumb2InstrInfo *TII;
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Thumb2 instruction size reduction pass";
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}
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private:
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead);
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bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry);
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bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry, bool LiveCPSR);
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/// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
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/// instruction.
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bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR);
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/// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
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/// non-two-address instruction.
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bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR);
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/// ReduceMBB - Reduce width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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};
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char Thumb2SizeReduce::ID = 0;
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}
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Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
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for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
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unsigned FromOpc = ReduceTable[i].WideOpc;
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if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
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assert(false && "Duplicated entries?");
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}
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}
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static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
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for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
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if (*Regs == ARM::CPSR)
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return true;
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return false;
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}
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bool
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Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead) {
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if ((is2Addr && Entry.PredCC2 == 0) ||
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(!is2Addr && Entry.PredCC1 == 0)) {
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if (Pred == ARMCC::AL) {
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// Not predicated, must set CPSR.
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if (!HasCC) {
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// Original instruction was not setting CPSR, but CPSR is not
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// currently live anyway. It's ok to set it. The CPSR def is
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// dead though.
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if (!LiveCPSR) {
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HasCC = true;
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CCDead = true;
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return true;
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}
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return false;
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}
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} else {
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// Predicated, must not set CPSR.
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if (HasCC)
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return false;
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}
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} else if ((is2Addr && Entry.PredCC2 == 2) ||
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(!is2Addr && Entry.PredCC1 == 2)) {
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/// Old opcode has an optional def of CPSR.
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if (HasCC)
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return true;
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// If both old opcode does not implicit CPSR def, then it's not ok since
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// these new opcodes CPSR def is not meant to be thrown away. e.g. CMP.
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if (!HasImplicitCPSRDef(MI->getDesc()))
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return false;
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HasCC = true;
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} else {
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// 16-bit instruction does not set CPSR.
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if (HasCC)
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return false;
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}
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return true;
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}
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static bool VerifyLowRegs(MachineInstr *MI) {
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unsigned Opc = MI->getOpcode();
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bool isPCOk = (Opc == ARM::t2LDM_RET) || (Opc == ARM::t2LDM);
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bool isLROk = (Opc == ARM::t2STM);
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bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isImplicit())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || Reg == ARM::CPSR)
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continue;
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if (isPCOk && Reg == ARM::PC)
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continue;
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if (isLROk && Reg == ARM::LR)
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continue;
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if (Reg == ARM::SP) {
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if (isSPOk)
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continue;
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if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
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// Special case for these ldr / str with sp as base register.
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continue;
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}
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if (!isARMLowRegister(Reg))
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return false;
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}
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry) {
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if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
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return false;
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unsigned Scale = 1;
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bool HasImmOffset = false;
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bool HasShift = false;
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bool HasOffReg = true;
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bool isLdStMul = false;
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unsigned Opc = Entry.NarrowOpc1;
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unsigned OpNum = 3; // First 'rest' of operands.
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uint8_t ImmLimit = Entry.Imm1Limit;
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switch (Entry.WideOpc) {
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default:
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llvm_unreachable("Unexpected Thumb2 load / store opcode!");
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case ARM::t2LDRi12:
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case ARM::t2STRi12: {
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unsigned BaseReg = MI->getOperand(1).getReg();
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if (BaseReg == ARM::SP) {
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Opc = Entry.NarrowOpc2;
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ImmLimit = Entry.Imm2Limit;
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HasOffReg = false;
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}
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Scale = 4;
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HasImmOffset = true;
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break;
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}
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case ARM::t2LDRBi12:
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case ARM::t2STRBi12:
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HasImmOffset = true;
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break;
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case ARM::t2LDRHi12:
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case ARM::t2STRHi12:
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Scale = 2;
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HasImmOffset = true;
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break;
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case ARM::t2LDRs:
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case ARM::t2LDRBs:
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case ARM::t2LDRHs:
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case ARM::t2LDRSBs:
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case ARM::t2LDRSHs:
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case ARM::t2STRs:
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case ARM::t2STRBs:
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case ARM::t2STRHs:
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HasShift = true;
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OpNum = 4;
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break;
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case ARM::t2LDM_RET:
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case ARM::t2LDM:
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case ARM::t2STM: {
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OpNum = 0;
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unsigned BaseReg = MI->getOperand(0).getReg();
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unsigned Mode = MI->getOperand(1).getImm();
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if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
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Opc = Entry.NarrowOpc2;
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OpNum = 2;
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} else if (Entry.WideOpc == ARM::t2LDM_RET ||
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!isARMLowRegister(BaseReg) ||
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!ARM_AM::getAM4WBFlag(Mode) ||
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ARM_AM::getAM4SubMode(Mode) != ARM_AM::ia) {
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return false;
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}
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isLdStMul = true;
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break;
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}
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}
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unsigned OffsetReg = 0;
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bool OffsetKill = false;
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if (HasShift) {
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OffsetReg = MI->getOperand(2).getReg();
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OffsetKill = MI->getOperand(2).isKill();
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if (MI->getOperand(3).getImm())
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// Thumb1 addressing mode doesn't support shift.
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return false;
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}
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unsigned OffsetImm = 0;
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if (HasImmOffset) {
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OffsetImm = MI->getOperand(2).getImm();
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unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
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if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
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// Make sure the immediate field fits.
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return false;
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}
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// Add the 16-bit load / store instruction.
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// FIXME: Thumb1 addressing mode encode both immediate and register offset.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
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if (!isLdStMul) {
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MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
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if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
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// tLDRSB and tLDRSH do not have an immediate offset field. On the other
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// hand, it must have an offset register.
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// FIXME: Remove this special case.
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MIB.addImm(OffsetImm/Scale);
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}
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assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
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if (HasOffReg)
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MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
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}
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// Transfer the rest of operands.
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for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
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MIB.addOperand(MI->getOperand(OpNum));
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// Transfer memoperands.
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(*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
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MBB.erase(MI);
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++NumLdSts;
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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if (Entry.LowRegs1 && !VerifyLowRegs(MI))
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return false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad() || TID.mayStore())
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return ReduceLoadStore(MBB, MI, Entry);
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::t2ADDSri:
|
|
case ARM::t2ADDSrr: {
|
|
unsigned PredReg = 0;
|
|
if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::t2ADDSri: {
|
|
if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
|
|
return true;
|
|
// fallthrough
|
|
}
|
|
case ARM::t2ADDSrr:
|
|
return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case ARM::t2RSBri:
|
|
case ARM::t2RSBSri:
|
|
if (MI->getOperand(2).getImm() == 0)
|
|
return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
|
|
break;
|
|
case ARM::t2MOVi16:
|
|
// Can convert only 'pure' immediate operands, not immediates obtained as
|
|
// globals' addresses.
|
|
if (MI->getOperand(1).isImm())
|
|
return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool
|
|
Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
|
|
const ReduceEntry &Entry,
|
|
bool LiveCPSR) {
|
|
|
|
if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
|
|
return false;
|
|
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
unsigned Reg0 = MI->getOperand(0).getReg();
|
|
unsigned Reg1 = MI->getOperand(1).getReg();
|
|
if (Reg0 != Reg1)
|
|
return false;
|
|
if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
|
|
return false;
|
|
if (Entry.Imm2Limit) {
|
|
unsigned Imm = MI->getOperand(2).getImm();
|
|
unsigned Limit = (1 << Entry.Imm2Limit) - 1;
|
|
if (Imm > Limit)
|
|
return false;
|
|
} else {
|
|
unsigned Reg2 = MI->getOperand(2).getReg();
|
|
if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
|
|
return false;
|
|
}
|
|
|
|
// Check if it's possible / necessary to transfer the predicate.
|
|
const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
|
|
unsigned PredReg = 0;
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
|
bool SkipPred = false;
|
|
if (Pred != ARMCC::AL) {
|
|
if (!NewTID.isPredicable())
|
|
// Can't transfer predicate, fail.
|
|
return false;
|
|
} else {
|
|
SkipPred = !NewTID.isPredicable();
|
|
}
|
|
|
|
bool HasCC = false;
|
|
bool CCDead = false;
|
|
if (TID.hasOptionalDef()) {
|
|
unsigned NumOps = TID.getNumOperands();
|
|
HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
|
|
if (HasCC && MI->getOperand(NumOps-1).isDead())
|
|
CCDead = true;
|
|
}
|
|
if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
|
|
return false;
|
|
|
|
// Add the 16-bit instruction.
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
|
|
MIB.addOperand(MI->getOperand(0));
|
|
if (NewTID.hasOptionalDef()) {
|
|
if (HasCC)
|
|
AddDefaultT1CC(MIB, CCDead);
|
|
else
|
|
AddNoT1CC(MIB);
|
|
}
|
|
|
|
// Transfer the rest of operands.
|
|
unsigned NumOps = TID.getNumOperands();
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
|
|
if (i < NumOps && TID.OpInfo[i].isOptionalDef())
|
|
continue;
|
|
if (SkipPred && TID.OpInfo[i].isPredicate())
|
|
continue;
|
|
MIB.addOperand(MI->getOperand(i));
|
|
}
|
|
|
|
DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
|
|
|
|
MBB.erase(MI);
|
|
++Num2Addrs;
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
|
|
const ReduceEntry &Entry,
|
|
bool LiveCPSR) {
|
|
if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
|
|
return false;
|
|
|
|
unsigned Limit = ~0U;
|
|
unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
|
|
if (Entry.Imm1Limit)
|
|
Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
|
|
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
|
|
if (TID.OpInfo[i].isPredicate())
|
|
continue;
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg()) {
|
|
unsigned Reg = MO.getReg();
|
|
if (!Reg || Reg == ARM::CPSR)
|
|
continue;
|
|
if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
|
|
continue;
|
|
if (Entry.LowRegs1 && !isARMLowRegister(Reg))
|
|
return false;
|
|
} else if (MO.isImm() &&
|
|
!TID.OpInfo[i].isPredicate()) {
|
|
if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Check if it's possible / necessary to transfer the predicate.
|
|
const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
|
|
unsigned PredReg = 0;
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
|
bool SkipPred = false;
|
|
if (Pred != ARMCC::AL) {
|
|
if (!NewTID.isPredicable())
|
|
// Can't transfer predicate, fail.
|
|
return false;
|
|
} else {
|
|
SkipPred = !NewTID.isPredicable();
|
|
}
|
|
|
|
bool HasCC = false;
|
|
bool CCDead = false;
|
|
if (TID.hasOptionalDef()) {
|
|
unsigned NumOps = TID.getNumOperands();
|
|
HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
|
|
if (HasCC && MI->getOperand(NumOps-1).isDead())
|
|
CCDead = true;
|
|
}
|
|
if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
|
|
return false;
|
|
|
|
// Add the 16-bit instruction.
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
|
|
MIB.addOperand(MI->getOperand(0));
|
|
if (NewTID.hasOptionalDef()) {
|
|
if (HasCC)
|
|
AddDefaultT1CC(MIB, CCDead);
|
|
else
|
|
AddNoT1CC(MIB);
|
|
}
|
|
|
|
// Transfer the rest of operands.
|
|
unsigned NumOps = TID.getNumOperands();
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
|
|
if (i < NumOps && TID.OpInfo[i].isOptionalDef())
|
|
continue;
|
|
if ((TID.getOpcode() == ARM::t2RSBSri ||
|
|
TID.getOpcode() == ARM::t2RSBri) && i == 2)
|
|
// Skip the zero immediate operand, it's now implicit.
|
|
continue;
|
|
bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
|
|
if (SkipPred && isPred)
|
|
continue;
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (Scale > 1 && !isPred && MO.isImm())
|
|
MIB.addImm(MO.getImm() / Scale);
|
|
else {
|
|
if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
|
|
// Skip implicit def of CPSR. Either it's modeled as an optional
|
|
// def now or it's already an implicit def on the new instruction.
|
|
continue;
|
|
MIB.addOperand(MO);
|
|
}
|
|
}
|
|
if (!TID.isPredicable() && NewTID.isPredicable())
|
|
AddDefaultPred(MIB);
|
|
|
|
DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
|
|
|
|
MBB.erase(MI);
|
|
++NumNarrows;
|
|
return true;
|
|
}
|
|
|
|
static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
|
|
bool HasDef = false;
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || MO.isUndef() || MO.isUse())
|
|
continue;
|
|
if (MO.getReg() != ARM::CPSR)
|
|
continue;
|
|
if (!MO.isDead())
|
|
HasDef = true;
|
|
}
|
|
|
|
return HasDef || LiveCPSR;
|
|
}
|
|
|
|
static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || MO.isUndef() || MO.isDef())
|
|
continue;
|
|
if (MO.getReg() != ARM::CPSR)
|
|
continue;
|
|
assert(LiveCPSR && "CPSR liveness tracking is wrong!");
|
|
if (MO.isKill()) {
|
|
LiveCPSR = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return LiveCPSR;
|
|
}
|
|
|
|
bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
|
|
bool LiveCPSR = false;
|
|
// Yes, CPSR could be livein.
|
|
for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
|
|
E = MBB.livein_end(); I != E; ++I) {
|
|
if (*I == ARM::CPSR) {
|
|
LiveCPSR = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
|
|
MachineBasicBlock::iterator NextMII;
|
|
for (; MII != E; MII = NextMII) {
|
|
NextMII = llvm::next(MII);
|
|
|
|
MachineInstr *MI = &*MII;
|
|
LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
|
|
if (OPI != ReduceOpcodeMap.end()) {
|
|
const ReduceEntry &Entry = ReduceTable[OPI->second];
|
|
// Ignore "special" cases for now.
|
|
if (Entry.Special) {
|
|
if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
|
|
Modified = true;
|
|
MachineBasicBlock::iterator I = prior(NextMII);
|
|
MI = &*I;
|
|
}
|
|
goto ProcessNext;
|
|
}
|
|
|
|
// Try to transform to a 16-bit two-address instruction.
|
|
if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
|
|
Modified = true;
|
|
MachineBasicBlock::iterator I = prior(NextMII);
|
|
MI = &*I;
|
|
goto ProcessNext;
|
|
}
|
|
|
|
// Try to transform ro a 16-bit non-two-address instruction.
|
|
if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR)) {
|
|
Modified = true;
|
|
MachineBasicBlock::iterator I = prior(NextMII);
|
|
MI = &*I;
|
|
}
|
|
}
|
|
|
|
ProcessNext:
|
|
LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
|
|
|
|
bool Modified = false;
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
|
|
Modified |= ReduceMBB(*I);
|
|
return Modified;
|
|
}
|
|
|
|
/// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
|
|
/// reduction pass.
|
|
FunctionPass *llvm::createThumb2SizeReductionPass() {
|
|
return new Thumb2SizeReduce();
|
|
}
|