mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-27 14:45:50 +00:00
3f2aee7e02
The commit after this changes { } and 0bxx literals to be of type bits<n> and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215082 91177308-0d34-0410-b5e6-96231b3b80d8
1228 lines
49 KiB
TableGen
1228 lines
49 KiB
TableGen
//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Sparc instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "SparcInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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// True when generating 32-bit code.
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def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
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// True when generating 64-bit code. This also implies HasV9.
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def Is64Bit : Predicate<"Subtarget.is64Bit()">;
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// HasV9 - This predicate is true when the target processor supports V9
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// instructions. Note that the machine may be running in 32-bit mode.
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def HasV9 : Predicate<"Subtarget.isV9()">,
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AssemblerPredicate<"FeatureV9">;
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// HasNoV9 - This predicate is true when the target doesn't have V9
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// instructions. Use of this is just a hack for the isel not having proper
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// costs for V8 instructions that are more expensive than their V9 ones.
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def HasNoV9 : Predicate<"!Subtarget.isV9()">;
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// HasVIS - This is true when the target processor has VIS extensions.
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def HasVIS : Predicate<"Subtarget.isVIS()">,
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AssemblerPredicate<"FeatureVIS">;
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def HasVIS2 : Predicate<"Subtarget.isVIS2()">,
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AssemblerPredicate<"FeatureVIS2">;
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def HasVIS3 : Predicate<"Subtarget.isVIS3()">,
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AssemblerPredicate<"FeatureVIS3">;
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// HasHardQuad - This is true when the target processor supports quad floating
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// point instructions.
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def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
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// UseDeprecatedInsts - This predicate is true when the target processor is a
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// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
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// to use when appropriate. In either of these cases, the instruction selector
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// will pick deprecated instructions.
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def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
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def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
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def LO10 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
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MVT::i32);
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}]>;
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def HI22 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
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}]>;
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def SETHIimm : PatLeaf<(imm), [{
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return isShiftedUInt<22, 10>(N->getZExtValue());
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}], HI22>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
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// Address operands
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def SparcMEMrrAsmOperand : AsmOperandClass {
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let Name = "MEMrr";
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let ParserMethod = "parseMEMOperand";
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}
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def SparcMEMriAsmOperand : AsmOperandClass {
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let Name = "MEMri";
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let ParserMethod = "parseMEMOperand";
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}
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def MEMrr : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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let ParserMatchClass = SparcMEMrrAsmOperand;
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}
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def MEMri : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, i32imm);
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let ParserMatchClass = SparcMEMriAsmOperand;
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}
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def TLSSym : Operand<iPTR>;
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValue";
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}
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def bprtarget : Operand<OtherVT> {
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let EncoderMethod = "getBranchPredTargetOpValue";
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}
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def bprtarget16 : Operand<OtherVT> {
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let EncoderMethod = "getBranchOnRegTargetOpValue";
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}
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def calltarget : Operand<i32> {
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let EncoderMethod = "getCallTargetOpValue";
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let DecoderMethod = "DecodeCall";
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}
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def simm13Op : Operand<i32> {
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let DecoderMethod = "DecodeSIMM13";
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}
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDTSPcmpicc :
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SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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def SDTSPcmpfcc :
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SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
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def SDTSPbrcc :
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SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def SDTSPselectcc :
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
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def SDTSPFTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDTSPITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDTSPFTOX :
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SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
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def SDTSPXTOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
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def SDTSPtlsadd :
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SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
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def SDTSPtlsld :
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SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
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def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
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def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
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def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
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def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
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def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
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def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
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def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
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def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
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def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
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def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
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def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
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def call : SDNode<"SPISD::CALL", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
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[SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
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def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
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def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
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def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def getPCX : Operand<iPTR> {
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let PrintMethod = "printGetPCX";
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}
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//===----------------------------------------------------------------------===//
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// SPARC Flag Conditions
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//===----------------------------------------------------------------------===//
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// Note that these values must be kept in sync with the CCOp::CondCode enum
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// values.
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class ICC_VAL<int N> : PatLeaf<(i32 N)>;
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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def ICC_LE : ICC_VAL< 2>; // Less or Equal
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def ICC_GE : ICC_VAL<11>; // Greater or Equal
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def ICC_L : ICC_VAL< 3>; // Less
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def ICC_GU : ICC_VAL<12>; // Greater Unsigned
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def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
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def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
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def ICC_POS : ICC_VAL<14>; // Positive
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def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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class FCC_VAL<int N> : PatLeaf<(i32 N)>;
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def FCC_U : FCC_VAL<23>; // Unordered
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def FCC_G : FCC_VAL<22>; // Greater
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def FCC_UG : FCC_VAL<21>; // Unordered or Greater
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def FCC_L : FCC_VAL<20>; // Less
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def FCC_UL : FCC_VAL<19>; // Unordered or Less
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def FCC_LG : FCC_VAL<18>; // Less or Greater
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def FCC_NE : FCC_VAL<17>; // Not Equal
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def FCC_E : FCC_VAL<25>; // Equal
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def FCC_UE : FCC_VAL<24>; // Unordered or Equal
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def FCC_GE : FCC_VAL<25>; // Greater or Equal
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def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
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def FCC_LE : FCC_VAL<27>; // Less or Equal
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def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<29>; // Ordered
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
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multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
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RegisterClass RC, ValueType Ty, Operand immOp> {
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def rr : F3_1<2, Op3Val,
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(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd"),
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[(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
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def ri : F3_2<2, Op3Val,
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(outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
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!strconcat(OpcStr, " $rs1, $simm13, $rd"),
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[(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
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}
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/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
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/// pattern.
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multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
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def rr : F3_1<2, Op3Val,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
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def ri : F3_2<2, Op3Val,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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!strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
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}
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// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
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multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
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RegisterClass RC, ValueType Ty> {
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def rr : F3_1<3, Op3Val,
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(outs RC:$dst), (ins MEMrr:$addr),
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!strconcat(OpcStr, " [$addr], $dst"),
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[(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
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def ri : F3_2<3, Op3Val,
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(outs RC:$dst), (ins MEMri:$addr),
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!strconcat(OpcStr, " [$addr], $dst"),
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[(set Ty:$dst, (OpNode ADDRri:$addr))]>;
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}
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// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
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multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
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RegisterClass RC, ValueType Ty> {
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def rr : F3_1<3, Op3Val,
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(outs), (ins MEMrr:$addr, RC:$rd),
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!strconcat(OpcStr, " $rd, [$addr]"),
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[(OpNode Ty:$rd, ADDRrr:$addr)]>;
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def ri : F3_2<3, Op3Val,
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(outs), (ins MEMri:$addr, RC:$rd),
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!strconcat(OpcStr, " $rd, [$addr]"),
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[(OpNode Ty:$rd, ADDRri:$addr)]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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// GETPCX for PIC
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let Defs = [O7] in {
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def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
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}
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let Defs = [O6], Uses = [O6] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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let hasSideEffects = 1, mayStore = 1 in {
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let rd = 0, rs1 = 0, rs2 = 0 in
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def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
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"flushw",
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[(flushw)]>, Requires<[HasV9]>;
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let rd = 0, rs1 = 1, simm13 = 3 in
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def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
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"ta 3",
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[(flushw)]>;
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}
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let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
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def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
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let rd = 0 in
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def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
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"unimp $imm22", []>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence. This has to handle all
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// permutations of selection between i32/f32/f64 on ICC and FCC.
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// Expanded after instruction selection.
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let Uses = [ICC], usesCustomInserter = 1 in {
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def SELECT_CC_Int_ICC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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[(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
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def SELECT_CC_DFP_ICC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_ICC PSEUDO!",
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[(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
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def SELECT_CC_QFP_ICC
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: Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_QFP_ICC PSEUDO!",
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[(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
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}
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let usesCustomInserter = 1, Uses = [FCC0] in {
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def SELECT_CC_Int_FCC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
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def SELECT_CC_FP_FCC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_FCC PSEUDO!",
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[(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
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def SELECT_CC_DFP_FCC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_FCC PSEUDO!",
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[(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
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def SELECT_CC_QFP_FCC
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: Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_QFP_FCC PSEUDO!",
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[(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
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}
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// JMPL Instruction.
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let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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DecoderMethod = "DecodeJMPL" in {
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def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
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"jmpl $addr, $dst", []>;
|
|
def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
|
|
"jmpl $addr, $dst", []>;
|
|
}
|
|
|
|
// Section A.3 - Synthetic Instructions, p. 85
|
|
// special cases of JMPL:
|
|
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
|
|
isCodeGenOnly = 1 in {
|
|
let rd = 0, rs1 = 15 in
|
|
def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
|
|
"jmp %o7+$val", [(retflag simm13:$val)]>;
|
|
|
|
let rd = 0, rs1 = 31 in
|
|
def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
|
|
"jmp %i7+$val", []>;
|
|
}
|
|
|
|
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
|
|
isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
|
|
def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
|
|
"rett $addr", []>;
|
|
def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
|
|
"rett $addr", []>;
|
|
}
|
|
|
|
// Section B.1 - Load Integer Instructions, p. 90
|
|
let DecoderMethod = "DecodeLoadInt" in {
|
|
defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
|
|
defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
|
|
defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
|
|
defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
|
|
defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
|
|
}
|
|
|
|
// Section B.2 - Load Floating-point Instructions, p. 92
|
|
let DecoderMethod = "DecodeLoadFP" in
|
|
defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
|
|
let DecoderMethod = "DecodeLoadDFP" in
|
|
defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
|
|
let DecoderMethod = "DecodeLoadQFP" in
|
|
defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
|
|
Requires<[HasV9, HasHardQuad]>;
|
|
|
|
// Section B.4 - Store Integer Instructions, p. 95
|
|
let DecoderMethod = "DecodeStoreInt" in {
|
|
defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
|
|
defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
|
|
defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
|
|
}
|
|
|
|
// Section B.5 - Store Floating-point Instructions, p. 97
|
|
let DecoderMethod = "DecodeStoreFP" in
|
|
defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
|
|
let DecoderMethod = "DecodeStoreDFP" in
|
|
defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
|
|
let DecoderMethod = "DecodeStoreQFP" in
|
|
defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
|
|
Requires<[HasV9, HasHardQuad]>;
|
|
|
|
// Section B.9 - SETHI Instruction, p. 104
|
|
def SETHIi: F2_1<0b100,
|
|
(outs IntRegs:$rd), (ins i32imm:$imm22),
|
|
"sethi $imm22, $rd",
|
|
[(set i32:$rd, SETHIimm:$imm22)]>;
|
|
|
|
// Section B.10 - NOP Instruction, p. 105
|
|
// (It's a special case of SETHI)
|
|
let rd = 0, imm22 = 0 in
|
|
def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
|
|
|
|
// Section B.11 - Logical Instructions, p. 106
|
|
defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
|
|
|
|
def ANDNrr : F3_1<2, 0b000101,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
|
"andn $rs1, $rs2, $rd",
|
|
[(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
|
|
def ANDNri : F3_2<2, 0b000101,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
|
|
"andn $rs1, $simm13, $rd", []>;
|
|
|
|
defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
|
|
|
|
def ORNrr : F3_1<2, 0b000110,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
|
"orn $rs1, $rs2, $rd",
|
|
[(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
|
|
def ORNri : F3_2<2, 0b000110,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
|
|
"orn $rs1, $simm13, $rd", []>;
|
|
defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
|
|
|
|
def XNORrr : F3_1<2, 0b000111,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
|
"xnor $rs1, $rs2, $rd",
|
|
[(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
|
|
def XNORri : F3_2<2, 0b000111,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
|
|
"xnor $rs1, $simm13, $rd", []>;
|
|
|
|
let Defs = [ICC] in {
|
|
defm ANDCC : F3_12np<"andcc", 0b010001>;
|
|
defm ANDNCC : F3_12np<"andncc", 0b010101>;
|
|
defm ORCC : F3_12np<"orcc", 0b010010>;
|
|
defm ORNCC : F3_12np<"orncc", 0b010110>;
|
|
defm XORCC : F3_12np<"xorcc", 0b010011>;
|
|
defm XNORCC : F3_12np<"xnorcc", 0b010111>;
|
|
}
|
|
|
|
// Section B.12 - Shift Instructions, p. 107
|
|
defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
|
|
defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
|
|
defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
|
|
|
|
// Section B.13 - Add Instructions, p. 108
|
|
defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
|
|
|
|
// "LEA" forms of add (patterns to make tblgen happy)
|
|
let Predicates = [Is32Bit], isCodeGenOnly = 1 in
|
|
def LEA_ADDri : F3_2<2, 0b000000,
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
|
"add ${addr:arith}, $dst",
|
|
[(set iPTR:$dst, ADDRri:$addr)]>;
|
|
|
|
let Defs = [ICC] in
|
|
defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
|
|
|
|
let Uses = [ICC] in
|
|
defm ADDC : F3_12np<"addx", 0b001000>;
|
|
|
|
let Uses = [ICC], Defs = [ICC] in
|
|
defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
|
|
|
|
// Section B.15 - Subtract Instructions, p. 110
|
|
defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
|
|
let Uses = [ICC], Defs = [ICC] in
|
|
defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
|
|
|
|
let Defs = [ICC] in
|
|
defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
|
|
|
|
let Uses = [ICC] in
|
|
defm SUBC : F3_12np <"subx", 0b001100>;
|
|
|
|
let Defs = [ICC], rd = 0 in {
|
|
def CMPrr : F3_1<2, 0b010100,
|
|
(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
|
|
"cmp $rs1, $rs2",
|
|
[(SPcmpicc i32:$rs1, i32:$rs2)]>;
|
|
def CMPri : F3_2<2, 0b010100,
|
|
(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
|
|
"cmp $rs1, $simm13",
|
|
[(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
|
|
}
|
|
|
|
// Section B.18 - Multiply Instructions, p. 113
|
|
let Defs = [Y] in {
|
|
defm UMUL : F3_12np<"umul", 0b001010>;
|
|
defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
|
|
}
|
|
|
|
let Defs = [Y, ICC] in {
|
|
defm UMULCC : F3_12np<"umulcc", 0b011010>;
|
|
defm SMULCC : F3_12np<"smulcc", 0b011011>;
|
|
}
|
|
|
|
// Section B.19 - Divide Instructions, p. 115
|
|
let Defs = [Y] in {
|
|
defm UDIV : F3_12np<"udiv", 0b001110>;
|
|
defm SDIV : F3_12np<"sdiv", 0b001111>;
|
|
}
|
|
|
|
let Defs = [Y, ICC] in {
|
|
defm UDIVCC : F3_12np<"udivcc", 0b011110>;
|
|
defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
|
|
}
|
|
|
|
// Section B.20 - SAVE and RESTORE, p. 117
|
|
defm SAVE : F3_12np<"save" , 0b111100>;
|
|
defm RESTORE : F3_12np<"restore", 0b111101>;
|
|
|
|
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
|
|
|
|
// unconditional branch class.
|
|
class BranchAlways<dag ins, string asmstr, list<dag> pattern>
|
|
: F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
let isBarrier = 1;
|
|
}
|
|
|
|
let cond = 8 in
|
|
def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
|
|
|
|
|
|
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
|
|
|
|
// conditional branch class:
|
|
class BranchSP<dag ins, string asmstr, list<dag> pattern>
|
|
: F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
|
|
|
|
// conditional branch with annul class:
|
|
class BranchSPA<dag ins, string asmstr, list<dag> pattern>
|
|
: F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
|
|
|
|
// Conditional branch class on %icc|%xcc with predication:
|
|
multiclass IPredBranch<string regstr, list<dag> CCPattern> {
|
|
def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
|
|
!strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
|
|
CCPattern>;
|
|
def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
|
|
!strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
|
|
[]>;
|
|
def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
|
|
!strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
|
|
[]>;
|
|
def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
|
|
!strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
|
|
[]>;
|
|
}
|
|
|
|
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
|
|
|
|
|
|
// Indirect branch instructions.
|
|
let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
|
|
isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
|
|
def BINDrr : F3_1<2, 0b111000,
|
|
(outs), (ins MEMrr:$ptr),
|
|
"jmp $ptr",
|
|
[(brind ADDRrr:$ptr)]>;
|
|
def BINDri : F3_2<2, 0b111000,
|
|
(outs), (ins MEMri:$ptr),
|
|
"jmp $ptr",
|
|
[(brind ADDRri:$ptr)]>;
|
|
}
|
|
|
|
let Uses = [ICC] in {
|
|
def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
|
|
"b$cond $imm22",
|
|
[(SPbricc bb:$imm22, imm:$cond)]>;
|
|
def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
|
|
"b$cond,a $imm22", []>;
|
|
|
|
let Predicates = [HasV9], cc = 0b00 in
|
|
defm BPI : IPredBranch<"%icc", []>;
|
|
}
|
|
|
|
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
|
|
|
|
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
|
|
|
|
// floating-point conditional branch class:
|
|
class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
|
|
: F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
|
|
|
|
// floating-point conditional branch with annul class:
|
|
class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
|
|
: F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
|
|
|
|
// Conditional branch class on %fcc0-%fcc3 with predication:
|
|
multiclass FPredBranch {
|
|
def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
|
|
FCCRegs:$cc),
|
|
"fb$cond $cc, $imm19", []>;
|
|
def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
|
|
FCCRegs:$cc),
|
|
"fb$cond,a $cc, $imm19", []>;
|
|
def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
|
|
FCCRegs:$cc),
|
|
"fb$cond,pn $cc, $imm19", []>;
|
|
def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
|
|
FCCRegs:$cc),
|
|
"fb$cond,a,pn $cc, $imm19", []>;
|
|
}
|
|
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
|
|
|
|
let Uses = [FCC0] in {
|
|
def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
|
|
"fb$cond $imm22",
|
|
[(SPbrfcc bb:$imm22, imm:$cond)]>;
|
|
def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
|
|
"fb$cond,a $imm22", []>;
|
|
}
|
|
|
|
let Predicates = [HasV9] in
|
|
defm BPF : FPredBranch;
|
|
|
|
|
|
// Section B.24 - Call and Link Instruction, p. 125
|
|
// This is the only Format 1 instruction
|
|
let Uses = [O6],
|
|
hasDelaySlot = 1, isCall = 1 in {
|
|
def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
|
|
"call $disp", []> {
|
|
bits<30> disp;
|
|
let op = 1;
|
|
let Inst{29-0} = disp;
|
|
}
|
|
|
|
// indirect calls: special cases of JMPL.
|
|
let isCodeGenOnly = 1, rd = 15 in {
|
|
def CALLrr : F3_1<2, 0b111000,
|
|
(outs), (ins MEMrr:$ptr, variable_ops),
|
|
"call $ptr",
|
|
[(call ADDRrr:$ptr)]>;
|
|
def CALLri : F3_2<2, 0b111000,
|
|
(outs), (ins MEMri:$ptr, variable_ops),
|
|
"call $ptr",
|
|
[(call ADDRri:$ptr)]>;
|
|
}
|
|
}
|
|
|
|
// Section B.28 - Read State Register Instructions
|
|
let Uses = [Y], rs1 = 0, rs2 = 0 in
|
|
def RDY : F3_1<2, 0b101000,
|
|
(outs IntRegs:$dst), (ins),
|
|
"rd %y, $dst", []>;
|
|
|
|
// Section B.29 - Write State Register Instructions
|
|
let Defs = [Y], rd = 0 in {
|
|
def WRYrr : F3_1<2, 0b110000,
|
|
(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
|
|
"wr $rs1, $rs2, %y", []>;
|
|
def WRYri : F3_2<2, 0b110000,
|
|
(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
|
|
"wr $rs1, $simm13, %y", []>;
|
|
}
|
|
// Convert Integer to Floating-point Instructions, p. 141
|
|
def FITOS : F3_3u<2, 0b110100, 0b011000100,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fitos $rs2, $rd",
|
|
[(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
|
|
def FITOD : F3_3u<2, 0b110100, 0b011001000,
|
|
(outs DFPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fitod $rs2, $rd",
|
|
[(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
|
|
def FITOQ : F3_3u<2, 0b110100, 0b011001100,
|
|
(outs QFPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fitoq $rs2, $rd",
|
|
[(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
// Convert Floating-point to Integer Instructions, p. 142
|
|
def FSTOI : F3_3u<2, 0b110100, 0b011010001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fstoi $rs2, $rd",
|
|
[(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
|
|
def FDTOI : F3_3u<2, 0b110100, 0b011010010,
|
|
(outs FPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fdtoi $rs2, $rd",
|
|
[(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
|
|
def FQTOI : F3_3u<2, 0b110100, 0b011010011,
|
|
(outs FPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fqtoi $rs2, $rd",
|
|
[(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
// Convert between Floating-point Formats Instructions, p. 143
|
|
def FSTOD : F3_3u<2, 0b110100, 0b011001001,
|
|
(outs DFPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fstod $rs2, $rd",
|
|
[(set f64:$rd, (fextend f32:$rs2))]>;
|
|
def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
|
|
(outs QFPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fstoq $rs2, $rd",
|
|
[(set f128:$rd, (fextend f32:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
def FDTOS : F3_3u<2, 0b110100, 0b011000110,
|
|
(outs FPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fdtos $rs2, $rd",
|
|
[(set f32:$rd, (fround f64:$rs2))]>;
|
|
def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
|
|
(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fdtoq $rs2, $rd",
|
|
[(set f128:$rd, (fextend f64:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
def FQTOS : F3_3u<2, 0b110100, 0b011000111,
|
|
(outs FPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fqtos $rs2, $rd",
|
|
[(set f32:$rd, (fround f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
def FQTOD : F3_3u<2, 0b110100, 0b011001011,
|
|
(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fqtod $rs2, $rd",
|
|
[(set f64:$rd, (fround f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
// Floating-point Move Instructions, p. 144
|
|
def FMOVS : F3_3u<2, 0b110100, 0b000000001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fmovs $rs2, $rd", []>;
|
|
def FNEGS : F3_3u<2, 0b110100, 0b000000101,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fnegs $rs2, $rd",
|
|
[(set f32:$rd, (fneg f32:$rs2))]>;
|
|
def FABSS : F3_3u<2, 0b110100, 0b000001001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fabss $rs2, $rd",
|
|
[(set f32:$rd, (fabs f32:$rs2))]>;
|
|
|
|
|
|
// Floating-point Square Root Instructions, p.145
|
|
def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fsqrts $rs2, $rd",
|
|
[(set f32:$rd, (fsqrt f32:$rs2))]>;
|
|
def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fsqrtd $rs2, $rd",
|
|
[(set f64:$rd, (fsqrt f64:$rs2))]>;
|
|
def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fsqrtq $rs2, $rd",
|
|
[(set f128:$rd, (fsqrt f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
|
|
|
|
// Floating-point Add and Subtract Instructions, p. 146
|
|
def FADDS : F3_3<2, 0b110100, 0b001000001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fadds $rs1, $rs2, $rd",
|
|
[(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
|
|
def FADDD : F3_3<2, 0b110100, 0b001000010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"faddd $rs1, $rs2, $rd",
|
|
[(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
|
|
def FADDQ : F3_3<2, 0b110100, 0b001000011,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"faddq $rs1, $rs2, $rd",
|
|
[(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
def FSUBS : F3_3<2, 0b110100, 0b001000101,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fsubs $rs1, $rs2, $rd",
|
|
[(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
|
|
def FSUBD : F3_3<2, 0b110100, 0b001000110,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fsubd $rs1, $rs2, $rd",
|
|
[(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
|
|
def FSUBQ : F3_3<2, 0b110100, 0b001000111,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fsubq $rs1, $rs2, $rd",
|
|
[(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
|
|
// Floating-point Multiply and Divide Instructions, p. 147
|
|
def FMULS : F3_3<2, 0b110100, 0b001001001,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fmuls $rs1, $rs2, $rd",
|
|
[(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
|
|
def FMULD : F3_3<2, 0b110100, 0b001001010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fmuld $rs1, $rs2, $rd",
|
|
[(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
|
|
def FMULQ : F3_3<2, 0b110100, 0b001001011,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fmulq $rs1, $rs2, $rd",
|
|
[(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
def FSMULD : F3_3<2, 0b110100, 0b001101001,
|
|
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fsmuld $rs1, $rs2, $rd",
|
|
[(set f64:$rd, (fmul (fextend f32:$rs1),
|
|
(fextend f32:$rs2)))]>;
|
|
def FDMULQ : F3_3<2, 0b110100, 0b001101110,
|
|
(outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fdmulq $rs1, $rs2, $rd",
|
|
[(set f128:$rd, (fmul (fextend f64:$rs1),
|
|
(fextend f64:$rs2)))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
def FDIVS : F3_3<2, 0b110100, 0b001001101,
|
|
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fdivs $rs1, $rs2, $rd",
|
|
[(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
|
|
def FDIVD : F3_3<2, 0b110100, 0b001001110,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fdivd $rs1, $rs2, $rd",
|
|
[(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
|
|
def FDIVQ : F3_3<2, 0b110100, 0b001001111,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fdivq $rs1, $rs2, $rd",
|
|
[(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
// Floating-point Compare Instructions, p. 148
|
|
// Note: the 2nd template arg is different for these guys.
|
|
// Note 2: the result of a FCMP is not available until the 2nd cycle
|
|
// after the instr is retired, but there is no interlock in Sparc V8.
|
|
// This behavior is modeled with a forced noop after the instruction in
|
|
// DelaySlotFiller.
|
|
|
|
let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
|
|
def FCMPS : F3_3c<2, 0b110101, 0b001010001,
|
|
(outs), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fcmps $rs1, $rs2",
|
|
[(SPcmpfcc f32:$rs1, f32:$rs2)]>;
|
|
def FCMPD : F3_3c<2, 0b110101, 0b001010010,
|
|
(outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fcmpd $rs1, $rs2",
|
|
[(SPcmpfcc f64:$rs1, f64:$rs2)]>;
|
|
def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
|
|
(outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fcmpq $rs1, $rs2",
|
|
[(SPcmpfcc f128:$rs1, f128:$rs2)]>,
|
|
Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions for Thread Local Storage(TLS).
|
|
//===----------------------------------------------------------------------===//
|
|
let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
|
|
def TLS_ADDrr : F3_1<2, 0b000000,
|
|
(outs IntRegs:$rd),
|
|
(ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
|
|
"add $rs1, $rs2, $rd, $sym",
|
|
[(set i32:$rd,
|
|
(tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
|
|
|
|
let mayLoad = 1 in
|
|
def TLS_LDrr : F3_1<3, 0b000000,
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
|
|
"ld [$addr], $dst, $sym",
|
|
[(set i32:$dst,
|
|
(tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
|
|
|
|
let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
|
|
def TLS_CALL : InstSP<(outs),
|
|
(ins calltarget:$disp, TLSSym:$sym, variable_ops),
|
|
"call $disp, $sym",
|
|
[(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
|
|
bits<30> disp;
|
|
let op = 1;
|
|
let Inst{29-0} = disp;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// V9 Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// V9 Conditional Moves.
|
|
let Predicates = [HasV9], Constraints = "$f = $rd" in {
|
|
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
|
let Uses = [ICC], intcc = 1, cc = 0b00 in {
|
|
def MOVICCrr
|
|
: F4_1<0b101100, (outs IntRegs:$rd),
|
|
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond %icc, $rs2, $rd",
|
|
[(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
|
|
|
|
def MOVICCri
|
|
: F4_2<0b101100, (outs IntRegs:$rd),
|
|
(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond %icc, $simm11, $rd",
|
|
[(set i32:$rd,
|
|
(SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
|
|
}
|
|
|
|
let Uses = [FCC0], intcc = 0, cc = 0b00 in {
|
|
def MOVFCCrr
|
|
: F4_1<0b101100, (outs IntRegs:$rd),
|
|
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond %fcc0, $rs2, $rd",
|
|
[(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
|
|
def MOVFCCri
|
|
: F4_2<0b101100, (outs IntRegs:$rd),
|
|
(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond %fcc0, $simm11, $rd",
|
|
[(set i32:$rd,
|
|
(SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
|
|
}
|
|
|
|
let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
|
|
def FMOVS_ICC
|
|
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
|
|
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
|
|
"fmovs$cond %icc, $rs2, $rd",
|
|
[(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
|
|
def FMOVD_ICC
|
|
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
|
|
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
|
|
"fmovd$cond %icc, $rs2, $rd",
|
|
[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
|
|
def FMOVQ_ICC
|
|
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
|
|
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
|
|
"fmovq$cond %icc, $rs2, $rd",
|
|
[(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
|
|
Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
|
|
def FMOVS_FCC
|
|
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
|
|
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
|
|
"fmovs$cond %fcc0, $rs2, $rd",
|
|
[(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
|
|
def FMOVD_FCC
|
|
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
|
|
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
|
|
"fmovd$cond %fcc0, $rs2, $rd",
|
|
[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
|
|
def FMOVQ_FCC
|
|
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
|
|
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
|
|
"fmovq$cond %fcc0, $rs2, $rd",
|
|
[(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
|
|
Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
}
|
|
|
|
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
|
let Predicates = [HasV9] in {
|
|
def FMOVD : F3_3u<2, 0b110100, 0b000000010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fmovd $rs2, $rd", []>;
|
|
def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fmovq $rs2, $rd", []>,
|
|
Requires<[HasHardQuad]>;
|
|
def FNEGD : F3_3u<2, 0b110100, 0b000000110,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fnegd $rs2, $rd",
|
|
[(set f64:$rd, (fneg f64:$rs2))]>;
|
|
def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fnegq $rs2, $rd",
|
|
[(set f128:$rd, (fneg f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
def FABSD : F3_3u<2, 0b110100, 0b000001010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fabsd $rs2, $rd",
|
|
[(set f64:$rd, (fabs f64:$rs2))]>;
|
|
def FABSQ : F3_3u<2, 0b110100, 0b000001011,
|
|
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fabsq $rs2, $rd",
|
|
[(set f128:$rd, (fabs f128:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
// Floating-point compare instruction with %fcc0-%fcc3.
|
|
def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
|
|
(outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fcmps $rd, $rs1, $rs2", []>;
|
|
def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
|
|
(outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fcmpd $rd, $rs1, $rs2", []>;
|
|
def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
|
|
(outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fcmpq $rd, $rs1, $rs2", []>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
let hasSideEffects = 1 in {
|
|
def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
|
|
(outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
|
|
"fcmpes $rd, $rs1, $rs2", []>;
|
|
def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
|
|
(outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
|
|
"fcmped $rd, $rs1, $rs2", []>;
|
|
def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
|
|
(outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
|
|
"fcmpeq $rd, $rs1, $rs2", []>,
|
|
Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
// Floating point conditional move instrucitons with %fcc0-%fcc3.
|
|
let Predicates = [HasV9] in {
|
|
let Constraints = "$f = $rd", intcc = 0 in {
|
|
def V9MOVFCCrr
|
|
: F4_1<0b101100, (outs IntRegs:$rd),
|
|
(ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond $cc, $rs2, $rd", []>;
|
|
def V9MOVFCCri
|
|
: F4_2<0b101100, (outs IntRegs:$rd),
|
|
(ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
|
|
"mov$cond $cc, $simm11, $rd", []>;
|
|
def V9FMOVS_FCC
|
|
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
|
|
(ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
|
|
"fmovs$cond $opf_cc, $rs2, $rd", []>;
|
|
def V9FMOVD_FCC
|
|
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
|
|
(ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
|
|
"fmovd$cond $opf_cc, $rs2, $rd", []>;
|
|
def V9FMOVQ_FCC
|
|
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
|
|
(ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
|
|
"fmovq$cond $opf_cc, $rs2, $rd", []>,
|
|
Requires<[HasHardQuad]>;
|
|
} // Constraints = "$f = $rd", ...
|
|
} // let Predicates = [hasV9]
|
|
|
|
|
|
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
|
|
// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
|
|
let rs1 = 0 in
|
|
def POPCrr : F3_1<2, 0b101110,
|
|
(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
"popc $src, $dst", []>, Requires<[HasV9]>;
|
|
def : Pat<(ctpop i32:$src),
|
|
(POPCrr (SRLri $src, 0))>;
|
|
|
|
// Atomic swap.
|
|
let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
|
|
def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
|
|
|
|
let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
|
|
def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
|
|
"membar $simm13", []>;
|
|
|
|
let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
|
|
def SWAPrr : F3_1<3, 0b001111,
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
|
|
"swap [$addr], $dst",
|
|
[(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
|
|
def SWAPri : F3_2<3, 0b001111,
|
|
(outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
|
|
"swap [$addr], $dst",
|
|
[(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
|
|
}
|
|
|
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let Predicates = [HasV9], Constraints = "$swap = $rd" in
|
|
def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
|
|
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
|
|
IntRegs:$swap),
|
|
"cas [$rs1], $rs2, $rd",
|
|
[(set i32:$rd,
|
|
(atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
|
|
|
|
let Defs = [ICC] in {
|
|
defm TADDCC : F3_12np<"taddcc", 0b100000>;
|
|
defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
|
|
|
|
let hasSideEffects = 1 in {
|
|
defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
|
|
defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
|
|
}
|
|
}
|
|
|
|
multiclass TRAP<string regStr> {
|
|
def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
|
|
CCOp:$cond),
|
|
!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
|
|
def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
|
|
CCOp:$cond),
|
|
!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
|
|
}
|
|
|
|
let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
|
|
defm TICC : TRAP<"%icc">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates.
|
|
def : Pat<(i32 simm13:$val),
|
|
(ORri (i32 G0), imm:$val)>;
|
|
// Arbitrary immediates.
|
|
def : Pat<(i32 imm:$val),
|
|
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
|
|
|
|
|
|
// Global addresses, constant pool entries
|
|
let Predicates = [Is32Bit] in {
|
|
|
|
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
|
|
def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
|
|
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
|
|
def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
|
|
|
|
// GlobalTLS addresses
|
|
def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
|
|
def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
|
|
def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
|
|
(ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
|
|
def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
|
|
(XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
|
|
|
|
// Blockaddress
|
|
def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
|
|
def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
|
|
|
|
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
|
|
def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
|
|
def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
|
|
def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
|
|
(ADDri $r, tblockaddress:$in)>;
|
|
}
|
|
|
|
// Calls:
|
|
def : Pat<(call tglobaladdr:$dst),
|
|
(CALL tglobaladdr:$dst)>;
|
|
def : Pat<(call texternalsym:$dst),
|
|
(CALL texternalsym:$dst)>;
|
|
|
|
// Map integer extload's to zextloads.
|
|
def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
|
def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
|
def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
|
|
def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
|
|
|
|
// zextload bool -> zextload byte
|
|
def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
|
|
|
// store 0, addr -> store %g0, addr
|
|
def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
|
|
def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
|
|
|
|
// store bar for all atomic_fence in V8.
|
|
let Predicates = [HasNoV9] in
|
|
def : Pat<(atomic_fence imm, imm), (STBAR)>;
|
|
|
|
// atomic_load_32 addr -> load addr
|
|
def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
|
|
def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
|
|
|
|
// atomic_store_32 val, addr -> store val, addr
|
|
def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
|
|
def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
|
|
|
|
|
|
include "SparcInstr64Bit.td"
|
|
include "SparcInstrVIS.td"
|
|
include "SparcInstrAliases.td"
|