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f262766619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26091 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.3 KiB
Plaintext
58 lines
1.3 KiB
Plaintext
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To-do
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-----
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* Keep the address of the constant pool in a register instead of forming its
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address all of the time.
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* We can fold small constant offsets into the %hi/%lo references to constant
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pool addresses as well.
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* When in V9 mode, register allocate %icc[0-3].
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* Emit the 'Branch on Integer Register with Prediction' instructions. It's
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not clear how to write a pattern for this though:
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float %t1(int %a, int* %p) {
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%C = seteq int %a, 0
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br bool %C, label %T, label %F
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T:
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store int 123, int* %p
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br label %F
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F:
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ret float undef
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}
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codegens to this:
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t1:
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save -96, %o6, %o6
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1) subcc %i0, 0, %l0
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1) bne .LBBt1_2 ! F
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nop
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.LBBt1_1: ! T
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or %g0, 123, %l0
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st %l0, [%i1]
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.LBBt1_2: ! F
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restore %g0, %g0, %g0
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retl
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nop
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1) should be replaced with a brz in V9 mode.
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* Same as above, but emit conditional move on register zero (p192) in V9
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mode. Testcase:
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int %t1(int %a, int %b) {
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%C = seteq int %a, 0
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%D = select bool %C, int %a, int %b
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ret int %D
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}
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* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
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with the Y register, if they are faster.
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* Codegen bswap(load)/store(bswap) -> load/store ASI
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* Implement frame pointer elimination, e.g. eliminate save/restore for
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leaf fns.
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* Fill delay slots
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