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715f7dd777
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274856 91177308-0d34-0410-b5e6-96231b3b80d8
934 lines
34 KiB
C++
Executable File
934 lines
34 KiB
C++
Executable File
//===------ LeonPasses.cpp - Define passes specific to LEON ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "LeonPasses.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
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: MachineFunctionPass(ID) {}
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LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
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: MachineFunctionPass(ID) {}
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int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr &MI,
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int OperandIndex) {
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if (MI.getNumOperands() > 0) {
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if (OperandIndex == LAST_OPERAND) {
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OperandIndex = MI.getNumOperands() - 1;
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}
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if (MI.getNumOperands() > (unsigned)OperandIndex &&
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MI.getOperand(OperandIndex).isReg()) {
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return (int)MI.getOperand(OperandIndex).getReg();
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}
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}
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static int NotFoundIndex = -10;
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// Return a different number each time to avoid any comparisons between the
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// values returned.
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NotFoundIndex -= 10;
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return NotFoundIndex;
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}
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// finds a new free FP register
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// checks also the AllocatedRegisters vector
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int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo &MRI) {
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for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) {
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if (!MRI.isPhysRegUsed(RegisterIndex) &&
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!(std::find(UsedRegisters.begin(), UsedRegisters.end(),
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RegisterIndex) != UsedRegisters.end())) {
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return RegisterIndex;
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}
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}
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return -1;
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}
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//*****************************************************************************
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//**** InsertNOPLoad pass
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//*****************************************************************************
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// This pass fixes the incorrectly working Load instructions that exists for
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// some earlier versions of the LEON processor line. NOP instructions must
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// be inserted after the load instruction to ensure that the Load instruction
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// behaves as expected for these processors.
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//
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// This pass inserts a NOP after any LD or LDF instruction.
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//
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char InsertNOPLoad::ID = 0;
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InsertNOPLoad::InsertNOPLoad(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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} else if (MI.isInlineAsm()) {
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// Look for an inline ld or ldf instruction.
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StringRef AsmString =
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MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
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if (AsmString.startswith_lower("ld")) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixFSMULD pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FSMULD instruction that exists for
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// some earlier versions of the LEON processor line.
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//
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// The pass should convert the FSMULD operands to double precision in scratch
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// registers, then calculate the result with the FMULD instruction. Therefore,
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// the pass should replace operations of the form:
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// fsmuld %f20,%f21,%f8
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// with the sequence:
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// fstod %f20,%f0
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// fstod %f21,%f2
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// fmuld %f0,%f2,%f8
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//
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char FixFSMULD::ID = 0;
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FixFSMULD::FixFSMULD(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
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bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) {
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// take the registers from fsmuld %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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} else if (MI.isInlineAsm()) {
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StringRef AsmString =
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MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
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if (AsmString.startswith_lower("fsmuld")) {
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// this is an inline FSMULD instruction
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unsigned StartOp = InlineAsm::MIOp_FirstOperand;
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// extracts the registers from the inline assembly instruction
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for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (Reg1Index == UNASSIGNED_INDEX)
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Reg1Index = MO.getReg();
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else if (Reg2Index == UNASSIGNED_INDEX)
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Reg2Index = MO.getReg();
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else if (Reg3Index == UNASSIGNED_INDEX)
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Reg3Index = MO.getReg();
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}
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if (Reg3Index != UNASSIGNED_INDEX)
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break;
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}
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}
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
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Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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// Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX ||
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ScratchReg2Index == UNASSIGNED_INDEX) {
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errs() << "Cannot allocate free scratch registers for the FixFSMULD "
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"pass."
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<< "\n";
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} else {
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// create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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// create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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// create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** ReplaceFMULS pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FMULS instruction that exists for
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// some earlier versions of the LEON processor line.
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//
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// This pass converts the FMULS operands to double precision in scratch
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// registers, then calculates the result with the FMULD instruction.
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// The pass should replace operations of the form:
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// fmuls %f20,%f21,%f8
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// with the sequence:
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// fstod %f20,%f0
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// fstod %f21,%f2
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// fmuld %f0,%f2,%f8
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//
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char ReplaceFMULS::ID = 0;
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ReplaceFMULS::ReplaceFMULS(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FMULS && MI.getNumOperands() == 3) {
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// take the registers from fmuls %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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} else if (MI.isInlineAsm()) {
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StringRef AsmString =
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MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
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if (AsmString.startswith_lower("fmuls")) {
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// this is an inline FMULS instruction
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unsigned StartOp = InlineAsm::MIOp_FirstOperand;
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// extracts the registers from the inline assembly instruction
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for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (Reg1Index == UNASSIGNED_INDEX)
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Reg1Index = MO.getReg();
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else if (Reg2Index == UNASSIGNED_INDEX)
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Reg2Index = MO.getReg();
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else if (Reg3Index == UNASSIGNED_INDEX)
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Reg3Index = MO.getReg();
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}
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if (Reg3Index != UNASSIGNED_INDEX)
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break;
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}
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}
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
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Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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// Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX ||
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ScratchReg2Index == UNASSIGNED_INDEX) {
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errs() << "Cannot allocate free scratch registers for the "
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"ReplaceFMULS pass."
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<< "\n";
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} else {
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// create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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// create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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// create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixAllFDIVSQRT pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FDIVx and FSQRTx instructions that
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// exist for some earlier versions of the LEON processor line. Five NOP
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// instructions need to be inserted after these instructions to ensure the
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// correct result is placed in the destination registers before they are used.
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//
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// This pass implements two fixes:
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// 1) fixing the FSQRTS and FSQRTD instructions.
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// 2) fixing the FDIVS and FDIVD instructions.
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//
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// FSQRTS and FDIVS are converted to FDIVD and FSQRTD respectively earlier in
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// the pipeline when this option is enabled, so this pass needs only to deal
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// with the changes that still need implementing for the "double" versions
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// of these instructions.
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//
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char FixAllFDIVSQRT::ID = 0;
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FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (MI.isInlineAsm()) {
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StringRef AsmString =
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MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
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if (AsmString.startswith_lower("fsqrtd")) {
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// this is an inline fsqrts instruction
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Opcode = SP::FSQRTD;
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} else if (AsmString.startswith_lower("fdivd")) {
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// this is an inline fsqrts instruction
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Opcode = SP::FDIVD;
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}
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}
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// Note: FDIVS and FSQRTS cannot be generated when this erratum fix is
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// switched on so we don't need to check for them here. They will
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// already have been converted to FSQRTD or FDIVD earlier in the
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// pipeline.
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if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
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// Insert 5 NOPs before FSQRTD,FDIVD.
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for (int InsertedCount = 0; InsertedCount < 5; InsertedCount++)
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BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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// ... and inserting 28 NOPs after FSQRTD,FDIVD.
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for (int InsertedCount = 0; InsertedCount < 28; InsertedCount++)
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** ReplaceSDIV pass
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//*****************************************************************************
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// This pass fixes the incorrectly working SDIV instruction that
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// exist for some earlier versions of the LEON processor line. The instruction
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// is replaced with an SDIVcc instruction instead, which is working.
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//
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char ReplaceSDIV::ID = 0;
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ReplaceSDIV::ReplaceSDIV() : LEONMachineFunctionPass(ID) {}
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ReplaceSDIV::ReplaceSDIV(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
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bool ReplaceSDIV::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (Opcode == SP::SDIVrr) {
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MI.setDesc(TII.get(SP::SDIVCCrr));
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Modified = true;
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} else if (Opcode == SP::SDIVri) {
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MI.setDesc(TII.get(SP::SDIVCCri));
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Modified = true;
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}
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}
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}
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return Modified;
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}
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static RegisterPass<ReplaceSDIV> X("replace-sdiv", "Replase SDIV Pass", false,
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false);
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//*****************************************************************************
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//**** FixCALL pass
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//*****************************************************************************
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// This pass restricts the size of the immediate operand of the CALL
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// instruction, which can cause problems on some earlier versions of the LEON
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// processor, which can interpret some of the call address bits incorrectly.
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//
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char FixCALL::ID = 0;
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FixCALL::FixCALL(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
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bool FixCALL::runOnMachineFunction(MachineFunction &MF) {
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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MI.print(errs());
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errs() << "\n";
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unsigned Opcode = MI.getOpcode();
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if (Opcode == SP::CALL || Opcode == SP::CALLrr) {
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unsigned NumOperands = MI.getNumOperands();
|
|
for (unsigned OperandIndex = 0; OperandIndex < NumOperands;
|
|
OperandIndex++) {
|
|
MachineOperand &MO = MI.getOperand(OperandIndex);
|
|
if (MO.isImm()) {
|
|
int64_t Value = MO.getImm();
|
|
MO.setImm(Value & 0x000fffffL);
|
|
Modified = true;
|
|
break;
|
|
}
|
|
}
|
|
} else if (MI.isInlineAsm()) // inline assembly immediate call
|
|
{
|
|
StringRef AsmString =
|
|
MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
|
|
if (AsmString.startswith_lower("call")) {
|
|
// this is an inline call instruction
|
|
unsigned StartOp = InlineAsm::MIOp_FirstOperand;
|
|
|
|
// extracts the registers from the inline assembly instruction
|
|
for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
if (MO.isImm()) {
|
|
int64_t Value = MO.getImm();
|
|
MO.setImm(Value & 0x000fffffL);
|
|
Modified = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//**** IgnoreZeroFlag pass
|
|
//*****************************************************************************
|
|
// This erratum fix fixes the overflow behavior of SDIVCC and UDIVCC
|
|
// instructions that exists on some earlier LEON processors. Where these
|
|
// instructions are detected, they are replaced by a sequence that will
|
|
// explicitly write the overflow bit flag if this is required.
|
|
//
|
|
char IgnoreZeroFlag::ID = 0;
|
|
|
|
IgnoreZeroFlag::IgnoreZeroFlag(TargetMachine &tm)
|
|
: LEONMachineFunctionPass(tm, ID) {}
|
|
|
|
bool IgnoreZeroFlag::runOnMachineFunction(MachineFunction &MF) {
|
|
Subtarget = &MF.getSubtarget<SparcSubtarget>();
|
|
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
|
|
DebugLoc DL = DebugLoc();
|
|
|
|
bool Modified = false;
|
|
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opcode = MI.getOpcode();
|
|
if (Opcode == SP::SDIVCCrr || Opcode == SP::SDIVCCri ||
|
|
Opcode == SP::UDIVCCrr || Opcode == SP::UDIVCCri) {
|
|
|
|
// split the current machine basic block - just after the sdivcc/udivcc
|
|
// instruction
|
|
// create a label that help us skip the zero flag update (of PSR -
|
|
// Processor Status Register)
|
|
// if conditions are not met
|
|
const BasicBlock *LLVM_BB = MBB.getBasicBlock();
|
|
MachineFunction::iterator It =
|
|
std::next(MachineFunction::iterator(MBB));
|
|
|
|
MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB);
|
|
MF.insert(It, dneBB);
|
|
|
|
// Transfer the remainder of MBB and its successor edges to dneBB.
|
|
dneBB->splice(dneBB->begin(), &MBB,
|
|
std::next(MachineBasicBlock::iterator(MI)), MBB.end());
|
|
dneBB->transferSuccessorsAndUpdatePHIs(&MBB);
|
|
|
|
MBB.addSuccessor(dneBB);
|
|
|
|
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
|
|
|
|
// bvc - branch if overflow flag not set
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
|
|
.addMBB(dneBB)
|
|
.addImm(SPCC::ICC_VS);
|
|
|
|
// bnz - branch if not zero
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
|
|
.addMBB(dneBB)
|
|
.addImm(SPCC::ICC_NE);
|
|
|
|
// use the WRPSR (Write Processor State Register) instruction to set the
|
|
// zeo flag to 1
|
|
// create wr %g0, 1, %psr
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri))
|
|
.addReg(SP::G0)
|
|
.addImm(1);
|
|
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::NOP));
|
|
|
|
Modified = true;
|
|
} else if (MI.isInlineAsm()) {
|
|
StringRef AsmString =
|
|
MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
|
|
if (AsmString.startswith_lower("sdivcc") ||
|
|
AsmString.startswith_lower("udivcc")) {
|
|
// this is an inline SDIVCC or UDIVCC instruction
|
|
|
|
// split the current machine basic block - just after the
|
|
// sdivcc/udivcc instruction
|
|
// create a label that help us skip the zero flag update (of PSR -
|
|
// Processor Status Register)
|
|
// if conditions are not met
|
|
const BasicBlock *LLVM_BB = MBB.getBasicBlock();
|
|
MachineFunction::iterator It =
|
|
std::next(MachineFunction::iterator(MBB));
|
|
|
|
MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB);
|
|
MF.insert(It, dneBB);
|
|
|
|
// Transfer the remainder of MBB and its successor edges to dneBB.
|
|
dneBB->splice(dneBB->begin(), &MBB,
|
|
std::next(MachineBasicBlock::iterator(MI)), MBB.end());
|
|
dneBB->transferSuccessorsAndUpdatePHIs(&MBB);
|
|
|
|
MBB.addSuccessor(dneBB);
|
|
|
|
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
|
|
|
|
// bvc - branch if overflow flag not set
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
|
|
.addMBB(dneBB)
|
|
.addImm(SPCC::ICC_VS);
|
|
|
|
// bnz - branch if not zero
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
|
|
.addMBB(dneBB)
|
|
.addImm(SPCC::ICC_NE);
|
|
|
|
// use the WRPSR (Write Processor State Register) instruction to set
|
|
// the zeo flag to 1
|
|
// create wr %g0, 1, %psr
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri))
|
|
.addReg(SP::G0)
|
|
.addImm(1);
|
|
|
|
BuildMI(MBB, NextMBBI, DL, TII.get(SP::NOP));
|
|
|
|
Modified = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//**** InsertNOPDoublePrecision pass
|
|
//*****************************************************************************
|
|
// This erratum fix for some earlier LEON processors fixes a problem where a
|
|
// double precision load will not yield the correct result if used in FMUL,
|
|
// FDIV, FADD, FSUB or FSQRT instructions later. If this sequence is detected,
|
|
// inserting a NOP between the two instructions will fix the erratum.
|
|
// 1.scans the code after register allocation;
|
|
// 2.checks for the problem conditions as described in the AT697E erratum
|
|
// “Odd-Numbered FPU Register Dependency not Properly Checked in some
|
|
// Double-Precision FPU Operations”;
|
|
// 3.inserts NOPs if the problem exists.
|
|
//
|
|
char InsertNOPDoublePrecision::ID = 0;
|
|
|
|
InsertNOPDoublePrecision::InsertNOPDoublePrecision(TargetMachine &tm)
|
|
: LEONMachineFunctionPass(tm, ID) {}
|
|
|
|
bool InsertNOPDoublePrecision::runOnMachineFunction(MachineFunction &MF) {
|
|
Subtarget = &MF.getSubtarget<SparcSubtarget>();
|
|
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
|
|
DebugLoc DL = DebugLoc();
|
|
|
|
bool Modified = false;
|
|
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opcode = MI.getOpcode();
|
|
if (Opcode == SP::LDDFri || Opcode == SP::LDDFrr) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
MachineInstr &NMI = *NMBBI;
|
|
|
|
unsigned NextOpcode = NMI.getOpcode();
|
|
// NMI.print(errs());
|
|
if (NextOpcode == SP::FADDD || NextOpcode == SP::FSUBD ||
|
|
NextOpcode == SP::FMULD || NextOpcode == SP::FDIVD) {
|
|
int RegAIndex = GetRegIndexForOperand(MI, 0);
|
|
int RegBIndex = GetRegIndexForOperand(NMI, 0);
|
|
int RegCIndex =
|
|
GetRegIndexForOperand(NMI, 2); // Second source operand is index 2
|
|
int RegDIndex =
|
|
GetRegIndexForOperand(NMI, 1); // Destination operand is index 1
|
|
|
|
if ((RegAIndex == RegBIndex + 1 && RegBIndex == RegDIndex) ||
|
|
(RegAIndex == RegCIndex + 1 && RegCIndex == RegDIndex) ||
|
|
(RegAIndex == RegBIndex + 1 && RegCIndex == RegDIndex) ||
|
|
(RegAIndex == RegCIndex + 1 && RegBIndex == RegDIndex)) {
|
|
// Insert NOP between the two instructions.
|
|
BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
|
|
Modified = true;
|
|
}
|
|
|
|
// Check the errata patterns that only happen for FADDD and FMULD
|
|
if (Modified == false &&
|
|
(NextOpcode == SP::FADDD || NextOpcode == SP::FMULD)) {
|
|
RegAIndex = GetRegIndexForOperand(MI, 1);
|
|
if (RegAIndex == RegBIndex + 1 && RegBIndex == RegCIndex &&
|
|
RegBIndex == RegDIndex) {
|
|
// Insert NOP between the two instructions.
|
|
BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
|
|
Modified = true;
|
|
}
|
|
}
|
|
} else if (NextOpcode == SP::FSQRTD) {
|
|
int RegAIndex = GetRegIndexForOperand(MI, 1);
|
|
int RegBIndex = GetRegIndexForOperand(NMI, 0);
|
|
int RegCIndex = GetRegIndexForOperand(NMI, 1);
|
|
|
|
if (RegAIndex == RegBIndex + 1 && RegBIndex == RegCIndex) {
|
|
// Insert NOP between the two instructions.
|
|
BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
|
|
Modified = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//**** PreventRoundChange pass
|
|
//*****************************************************************************
|
|
// To prevent any explicit change of the default rounding mode, this pass
|
|
// detects any call of the fesetround function and removes this call from the
|
|
// list of generated operations.
|
|
//
|
|
char PreventRoundChange::ID = 0;
|
|
|
|
PreventRoundChange::PreventRoundChange(TargetMachine &tm)
|
|
: LEONMachineFunctionPass(tm, ID) {}
|
|
|
|
bool PreventRoundChange::runOnMachineFunction(MachineFunction &MF) {
|
|
Subtarget = &MF.getSubtarget<SparcSubtarget>();
|
|
|
|
bool Modified = false;
|
|
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opcode = MI.getOpcode();
|
|
if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
|
|
MachineOperand &MO = MI.getOperand(0);
|
|
|
|
if (MO.isGlobal()) {
|
|
StringRef FuncName = MO.getGlobal()->getName();
|
|
if (FuncName.compare_lower("fesetround") == 0) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
MI.eraseFromParent();
|
|
MBBI = NMBBI;
|
|
Modified = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
//*****************************************************************************
|
|
//**** FlushCacheLineSWAP pass
|
|
//*****************************************************************************
|
|
// This pass inserts FLUSHW just before any SWAP atomic instruction.
|
|
//
|
|
char FlushCacheLineSWAP::ID = 0;
|
|
|
|
FlushCacheLineSWAP::FlushCacheLineSWAP(TargetMachine &tm)
|
|
: LEONMachineFunctionPass(tm, ID) {}
|
|
|
|
bool FlushCacheLineSWAP::runOnMachineFunction(MachineFunction &MF) {
|
|
Subtarget = &MF.getSubtarget<SparcSubtarget>();
|
|
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
|
|
DebugLoc DL = DebugLoc();
|
|
|
|
bool Modified = false;
|
|
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opcode = MI.getOpcode();
|
|
if (Opcode == SP::SWAPrr || Opcode == SP::SWAPri ||
|
|
Opcode == SP::LDSTUBrr || Opcode == SP::LDSTUBri) {
|
|
// insert flush and 5 NOPs before the swap/ldstub instruction
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::FLUSH));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
|
|
Modified = true;
|
|
} else if (MI.isInlineAsm()) {
|
|
StringRef AsmString =
|
|
MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
|
|
if (AsmString.startswith_lower("swap") ||
|
|
AsmString.startswith_lower("ldstub")) {
|
|
// this is an inline swap or ldstub instruction
|
|
|
|
// insert flush and 5 NOPs before the swap/ldstub instruction
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::FLUSH));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
|
|
Modified = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//**** InsertNOPsLoadStore pass
|
|
//*****************************************************************************
|
|
// This pass shall insert NOPs between floating point loads and stores when the
|
|
// following circumstances are present [5]:
|
|
// Pattern 1:
|
|
// 1. single-precision load or single-precision FPOP to register %fX, where X is
|
|
// the same register as the store being checked;
|
|
// 2. single-precision load or single-precision FPOP to register %fY , where Y
|
|
// is the opposite register in the same double-precision pair;
|
|
// 3. 0-3 instructions of any kind, except stores from %fX or %fY or operations
|
|
// with %fX as destination;
|
|
// 4. the store (from register %fX) being considered.
|
|
// Pattern 2:
|
|
// 1. double-precision FPOP;
|
|
// 2. any number of operations on any kind, except no double-precision FPOP and
|
|
// at most one (less than two) single-precision or single-to-double FPOPs;
|
|
// 3. the store (from register %fX) being considered.
|
|
//
|
|
char InsertNOPsLoadStore::ID = 0;
|
|
|
|
InsertNOPsLoadStore::InsertNOPsLoadStore(TargetMachine &tm)
|
|
: LEONMachineFunctionPass(tm, ID) {}
|
|
|
|
bool InsertNOPsLoadStore::runOnMachineFunction(MachineFunction &MF) {
|
|
Subtarget = &MF.getSubtarget<SparcSubtarget>();
|
|
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
|
|
DebugLoc DL = DebugLoc();
|
|
|
|
MachineInstr *Pattern1FirstInstruction = NULL;
|
|
MachineInstr *Pattern2FirstInstruction = NULL;
|
|
unsigned int StoreInstructionsToCheck = 0;
|
|
int FxRegIndex, FyRegIndex;
|
|
|
|
bool Modified = false;
|
|
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
|
|
if (StoreInstructionsToCheck > 0) {
|
|
if (((MI.getOpcode() == SP::STFrr || MI.getOpcode() == SP::STFri) &&
|
|
(GetRegIndexForOperand(MI, LAST_OPERAND) == FxRegIndex ||
|
|
GetRegIndexForOperand(MI, LAST_OPERAND) == FyRegIndex)) ||
|
|
GetRegIndexForOperand(MI, 0) == FxRegIndex) {
|
|
// Insert four NOPs
|
|
for (unsigned InsertedCount = 0; InsertedCount < 4; InsertedCount++) {
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
}
|
|
Modified = true;
|
|
}
|
|
StoreInstructionsToCheck--;
|
|
}
|
|
|
|
switch (MI.getOpcode()) {
|
|
// Watch for Pattern 1 FPop instructions
|
|
case SP::LDrr:
|
|
case SP::LDri:
|
|
case SP::LDFrr:
|
|
case SP::LDFri:
|
|
case SP::FADDS:
|
|
case SP::FSUBS:
|
|
case SP::FMULS:
|
|
case SP::FDIVS:
|
|
case SP::FSQRTS:
|
|
case SP::FCMPS:
|
|
case SP::FMOVS:
|
|
case SP::FNEGS:
|
|
case SP::FABSS:
|
|
case SP::FITOS:
|
|
case SP::FSTOI:
|
|
case SP::FITOD:
|
|
case SP::FDTOI:
|
|
case SP::FDTOS:
|
|
if (Pattern1FirstInstruction != NULL) {
|
|
FxRegIndex = GetRegIndexForOperand(*Pattern1FirstInstruction, 0);
|
|
FyRegIndex = GetRegIndexForOperand(MI, 0);
|
|
|
|
// Check to see if these registers are part of the same double
|
|
// precision
|
|
// register pair.
|
|
int DoublePrecRegIndexForX = (FxRegIndex - SP::F0) / 2;
|
|
int DoublePrecRegIndexForY = (FyRegIndex - SP::F0) / 2;
|
|
|
|
if (DoublePrecRegIndexForX == DoublePrecRegIndexForY)
|
|
StoreInstructionsToCheck = 4;
|
|
}
|
|
|
|
Pattern1FirstInstruction = &MI;
|
|
break;
|
|
// End of Pattern 1
|
|
|
|
// Search for Pattern 2
|
|
case SP::FADDD:
|
|
case SP::FSUBD:
|
|
case SP::FMULD:
|
|
case SP::FDIVD:
|
|
case SP::FSQRTD:
|
|
case SP::FCMPD:
|
|
Pattern2FirstInstruction = &MI;
|
|
Pattern1FirstInstruction = NULL;
|
|
break;
|
|
|
|
case SP::STFrr:
|
|
case SP::STFri:
|
|
case SP::STDFrr:
|
|
case SP::STDFri:
|
|
if (Pattern2FirstInstruction != NULL) {
|
|
if (GetRegIndexForOperand(MI, LAST_OPERAND) ==
|
|
GetRegIndexForOperand(*Pattern2FirstInstruction, 0)) {
|
|
// Insert four NOPs
|
|
for (unsigned InsertedCount = 0; InsertedCount < 4;
|
|
InsertedCount++) {
|
|
BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
|
|
}
|
|
|
|
Pattern2FirstInstruction = NULL;
|
|
}
|
|
}
|
|
Pattern1FirstInstruction = NULL;
|
|
break;
|
|
// End of Pattern 2
|
|
|
|
default:
|
|
// Ensure we don't count debug-only values while we're testing for the
|
|
// patterns.
|
|
if (!MI.isDebugValue())
|
|
Pattern1FirstInstruction = NULL;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|