Simon Pilgrim d0fe19165f [SLPVectorizer] Flag ADD/SUB SSAT/USAT intrinsics trivially vectorizable (PR40123) ...

Enables SLP vectorization for the SSE2 PADDS/PADDUS/PSUBS/PSUBUS style intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350300 91177308-0d34-0410-b5e6-96231b3b80d8

2019-01-03 12:18:23 +00:00

..

AArch64

[SLPVectorizer] regenerate test checks; NFC

2018-10-20 14:53:07 +00:00

AMDGPU

Fix vectorization of canonicalize

2018-09-17 13:24:30 +00:00

ARM

[SLPVectorizer] add test for PR13837; NFC

2018-01-23 22:04:17 +00:00

NVPTX

[NVPTX] Turn on Loop/SLP vectorization

2018-04-27 13:36:05 +00:00

PowerPC

[SLP] Update tests checks, NFC.

2018-01-05 14:40:04 +00:00

SystemZ

[SLPVectorizer] Add tests related to PR30787, NFCI.

2018-03-29 18:57:03 +00:00

X86

[SLPVectorizer] Flag ADD/SUB SSAT/USAT intrinsics trivially vectorizable (PR40123)

2019-01-03 12:18:23 +00:00

XCore

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

int_sideeffect.ll

Add an @llvm.sideeffect intrinsic

2017-11-08 21:59:51 +00:00