Lewis Revill f5bddce9ea [RISCV] Add pseudo instruction for calls with explicit register ... This patch adds the PseudoCALLReg instruction which allows using an explicit register operand as the destination for the return address. GCC can successfully parse this form of the call instruction, which would be used for calls to functions which do not use ra as the return address register, such as the __riscv_save libcalls. This patch forms the first part of an implementation of -msave-restore for RISC-V. Differential Revision: https://reviews.llvm.org/D62685 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364403 91177308-0d34-0410-b5e6-96231b3b80d8		2019-06-26 10:35:58 +00:00
..
align.s	[RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled	2019-01-30 11:16:59 +00:00
cfi-regs-invalid.s	[RISCV] Fix RISCVAsmParser::ParseRegister and add tests	2019-03-17 12:00:58 +00:00
cfi-regs-valid.s	[RISCV] Fix RISCVAsmParser::ParseRegister and add tests	2019-03-17 12:00:58 +00:00
cnop.s
compress-cjal.s
compress-rv32d.s
compress-rv32f.s
compress-rv32i.s	[RISCV] Add UNIMP instruction (32- and 16-bit forms)	2018-11-30 13:39:17 +00:00
compress-rv64i.s
compressed-relocations.s
csr-aliases.s	[RISCV] Allow access to FP CSRs without F extension	2019-03-08 23:01:08 +00:00
data-directives-invalid.s
data-directives-valid.s
elf-flags.s	[llvm-readobj] Change -long-option to --long-option in tests. NFC	2019-05-01 05:27:20 +00:00
elf-header.s
empty-string.s	Move some llvm-mc tests where they belong	2019-02-05 20:12:48 +00:00
fixups-compressed.s
fixups-diagnostics.s
fixups-expr.s
fixups.s	[RISCV] Properly evaluate fixup_riscv_pcrel_lo12	2018-12-20 14:52:15 +00:00
function-call-invalid.s	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
function-call.s	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
hilo-constaddr-expr.s
hilo-constaddr.s
linker-relaxation.s	[RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation)	2019-04-01 02:38:27 +00:00
lit.local.cfg	[lit] Delete empty lines at the end of lit.local.cfg NFC	2019-06-17 09:51:07 +00:00
lla-invalid.s	[RISCV] Support assembling @plt symbol operands	2019-04-02 12:47:20 +00:00
machine-csr-names-invalid.s
machine-csr-names.s
mattr-invalid-combination.s	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
option-invalid.s	[RISCV] Support .option push and .option pop	2018-11-28 16:39:14 +00:00
option-mix.s	[RISCV][MC] Find matching pcrel_hi fixup in more cases.	2019-03-12 18:14:16 +00:00
option-pushpop.s	[RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates.	2019-01-21 05:27:09 +00:00
option-relax.s	[RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation)	2019-04-01 02:38:27 +00:00
option-rvc.s
pcrel-lo12-invalid.s	[RISCV] Properly evaluate fixup_riscv_pcrel_lo12	2018-12-20 14:52:15 +00:00
priv-invalid.s
priv-valid.s
relocations.s	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
rv32-machine-csr-names.s
rv32-relaxation.s
rv32-user-csr-names.s
rv32a-invalid.s
rv32a-valid.s
rv32c-aliases-valid.s
rv32c-fuzzed-invalid.s
rv32c-invalid.s
rv32c-only-valid.s
rv32c-valid.s	[RISCV] Add UNIMP instruction (32- and 16-bit forms)	2018-11-30 13:39:17 +00:00
rv32d-invalid.s	[RISCV] Support assembling TLS add and associated modifiers	2019-04-04 14:13:37 +00:00
rv32d-valid.s
rv32dc-invalid.s
rv32dc-valid.s
rv32e-invalid.s	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
rv32e-valid.s	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
rv32f-invalid.s	[RISCV] Support assembling TLS add and associated modifiers	2019-04-04 14:13:37 +00:00
rv32f-valid.s
rv32fc-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rv32fc-invalid.s
rv32fc-valid.s
rv32i-aliases-invalid.s
rv32i-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rv32i-invalid.s	[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers	2019-04-23 14:46:13 +00:00
rv32i-valid.s	[RISCV] Allow parsing immediates that use tilde & exclaim	2019-06-19 10:27:24 +00:00
rv32m-invalid.s
rv32m-valid.s
rv64-machine-csr-names.s
rv64-relaxation.s
rv64-user-csr-names.s
rv64a-invalid.s
rv64a-valid.s
rv64c-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rv64c-invalid.s
rv64c-valid.s
rv64d-aliases-valid.s
rv64d-invalid.s
rv64d-valid.s
rv64dc-valid.s
rv64f-aliases-valid.s
rv64f-invalid.s
rv64f-valid.s
rv64i-aliases-invalid.s
rv64i-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rv64i-invalid.s	[RISCV] Support assembling TLS add and associated modifiers	2019-04-04 14:13:37 +00:00
rv64i-pseudos.s	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
rv64i-valid.s	[RISCV][MC] Add support for evaluating constant symbols as immediates	2019-01-10 15:33:17 +00:00
rv64m-valid.s
rvc-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rvd-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rvd-pseudos.s	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
rvdc-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rvf-aliases-valid.s	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
rvf-pseudos.s	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
rvf-user-csr-names.s	[RISCV] Allow access to FP CSRs without F extension	2019-03-08 23:01:08 +00:00
rvi-aliases-valid.s	[RISCV] Add additional CSR instruction aliases (imm. operands)	2018-11-30 14:10:52 +00:00
rvi-alternate-abi-names.s	[RISCV] Allow fp as an alias of s0	2019-03-11 21:35:26 +00:00
rvi-pseudos-invalid.s	[RISCV] Support assembling TLS add and associated modifiers	2019-04-04 14:13:37 +00:00
rvi-pseudos.s	[RISCV] Support assembling TLS LA pseudo instructions	2019-05-23 14:46:27 +00:00
supervisor-csr-names.s
tail-call-invalid.s
tail-call.s	[RISCV] Support assembling @plt symbol operands	2019-04-02 12:47:20 +00:00
target-abi-invalid.s	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
target-abi-valid.s	[llvm-readobj] Change -long-option to --long-option in tests. NFC	2019-05-01 05:27:20 +00:00
user-csr-names-invalid.s	[RISCV] Allow access to FP CSRs without F extension	2019-03-08 23:01:08 +00:00
user-csr-names.s