Richard Sandiford c2b840cb7c [SystemZ] Add instruction-shortening pass ... When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-25 10:11:07 +00:00
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CMakeLists.txt
LLVMBuild.txt
Makefile
SystemZMCAsmBackend.cpp	Generate compact unwind encoding from CFI directives.	2013-09-09 02:37:14 +00:00
SystemZMCAsmInfo.cpp	MC: Remove vestigial PCSymbol field from AsmInfo	2013-09-25 09:36:11 +00:00
SystemZMCAsmInfo.h	Remove unused argument.	2013-05-10 18:16:59 +00:00
SystemZMCCodeEmitter.cpp	[SystemZ] Add the MVC instruction	2013-07-02 14:56:45 +00:00
SystemZMCFixups.h
SystemZMCObjectWriter.cpp
SystemZMCTargetDesc.cpp	[SystemZ] Add instruction-shortening pass	2013-09-25 10:11:07 +00:00
SystemZMCTargetDesc.h	[SystemZ] Add instruction-shortening pass	2013-09-25 10:11:07 +00:00