llvm/lib at a0f14afee16ca976fef79c64df9a678e7f26cf43 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-01-17 15:33:45 +00:00

History

Jack Carter a0f14afee1 Mips specific inline asm operand modifier 'M':

Print the high order register of a double word register operand.

In 32 bit mode, a 64 bit double word integer will be represented
by 2 32 bit registers. This modifier causes the high order register
to be used in the asm expression. It is useful if you are using 
doubles in assembler and continue to control register to variable
relationships.

This patch also fixes a related bug in a previous patch:

    case 'D': // Second part of a double word register operand
    case 'L': // Low order register of a double word register operand
    case 'M': // High order register of a double word register operand

I got 'D' and 'M' confused. The second part of a double word operand
will only match 'M' for one of the endianesses. I had 'L' and 'D'
be the opposite twins when 'L' and 'M' are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8

2012-07-18 06:41:36 +00:00

Analysis

Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completes

2012-07-15 23:45:24 +00:00

Archive

Include cstdio in a few place that depended on getting it transitively through StringExtras.h

2012-03-23 11:35:30 +00:00

AsmParser

Extend the IL for selecting TLS models (PR9788)

2012-06-23 11:37:03 +00:00

Bitcode

llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.