Tim Northover a10c01a6c6 ARM: relax the atomic release barrier to "dmb ishst" on Swift ... Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-03 09:20:36 +00:00
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Analysis	Minimize precision loss when computing cyclic probabilities.	2013-06-28 22:40:43 +00:00
Archive
Assembler	Added support for the Builtin attribute.	2013-06-27 00:25:01 +00:00
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	ARM: relax the atomic release barrier to "dmb ishst" on Swift	2013-07-03 09:20:36 +00:00
DebugInfo	Trying to fix the bots	2013-07-03 00:16:11 +00:00
ExecutionEngine
Feature
FileCheck
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Integer
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MC	[PowerPC] PR16512 - Support TLS call sequences in the asm parser	2013-07-02 21:31:59 +00:00
Object
Other	(1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.	2013-07-01 18:58:53 +00:00
TableGen
tools
Transforms	Change the gettimeofday test to only test on a posix platform.	2013-07-03 04:15:22 +00:00
Unit
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YAMLParser
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