Tim Northover 4951996d06 GlobalISel: implement low-level type with just size & vector lanes. ...

This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276158 91177308-0d34-0410-b5e6-96231b3b80d8

2016-07-20 19:09:30 +00:00

..

CMakeLists.txt

MIR Serialization: Introduce a lexer for machine instructions.

2015-06-22 20:37:46 +00:00

LLVMBuild.txt

MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum().

2015-07-24 01:12:36 +00:00

MILexer.cpp

GlobalISel: implement low-level type with just size & vector lanes.

2016-07-20 19:09:30 +00:00

MILexer.h

GlobalISel: implement low-level type with just size & vector lanes.

2016-07-20 19:09:30 +00:00

MIParser.cpp

GlobalISel: implement low-level type with just size & vector lanes.

2016-07-20 19:09:30 +00:00

MIParser.h

MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFC

2016-07-13 23:27:50 +00:00

MIRParser.cpp

MIRParser: Fix MIRParser not reporting nullptr on error.

2016-07-14 00:42:37 +00:00