Bradley Smith a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-09 14:42:11 +00:00

..

AArch64

PR18929:

2014-03-30 17:09:54 +00:00

ARM

Fix the ARM VLD3 (single 3-element structure to all lanes)

2014-04-08 18:00:52 +00:00

ARM64

[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)

2014-04-09 14:42:07 +00:00

AsmParser

Move tests that require ARM to an ARM test directory.

2014-03-18 22:43:59 +00:00

COFF

WinCOFF: Emit common symbols as specified in the COFF spec

2014-04-08 22:33:40 +00:00

Disassembler

[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

2014-04-09 14:42:11 +00:00

ELF

X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.

2014-04-08 15:28:50 +00:00

MachO

ARM: consolidate MachO checks for ARM asm parser

2014-04-05 22:09:51 +00:00

Markup

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Mips

[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.

2014-04-04 16:21:59 +00:00

PowerPC

[PowerPC] Generate little-endian object files

2014-03-24 18:16:09 +00:00

Sparc

[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.

2014-03-02 23:39:07 +00:00

SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

X86

AVX-512: Implemented masking for integer arithmetic & logic instructions.

2014-03-27 09:45:08 +00:00