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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24763 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.5 KiB
Plaintext
110 lines
3.5 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend.
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//===---------------------------------------------------------------------===//
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Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
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Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
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X86, & make the dag combiner produce it when needed. This will eliminate one
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imul from the code generated for:
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long long test(long long X, long long Y) { return X*Y; }
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by using the EAX result from the mul. We should add a similar node for
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DIVREM.
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another case is:
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long long test(int X, int Y) { return (long long)X*Y; }
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... which should only be one imul instruction.
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//===---------------------------------------------------------------------===//
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This should be one DIV/IDIV instruction, not a libcall:
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unsigned test(unsigned long long X, unsigned Y) {
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return X/Y;
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}
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This can be done trivially with a custom legalizer. What about overflow
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though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
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//===---------------------------------------------------------------------===//
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Need to add support for rotate instructions.
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//===---------------------------------------------------------------------===//
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Some targets (e.g. athlons) prefer freep to fstp ST(0):
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http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html
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//===---------------------------------------------------------------------===//
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This should use faddi on chips where it is profitable:
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double foo(double P, int *I) { return P+*I; }
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//===---------------------------------------------------------------------===//
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The FP stackifier needs to be global. Also, it should handle simple permutates
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to reduce number of shuffle instructions, e.g. turning:
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fld P -> fld Q
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fld Q fld P
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fxch
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or:
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fxch -> fucomi
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fucomi jl X
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jg X
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//===---------------------------------------------------------------------===//
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Improvements to the multiply -> shift/add algorithm:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
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//===---------------------------------------------------------------------===//
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Improve code like this (occurs fairly frequently, e.g. in LLVM):
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long long foo(int x) { return 1LL << x; }
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
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Another useful one would be ~0ULL >> X and ~0ULL << X.
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//===---------------------------------------------------------------------===//
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Should support emission of the bswap instruction, probably by adding a new
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DAG node for byte swapping. Also useful on PPC which has byte-swapping loads.
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//===---------------------------------------------------------------------===//
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Compile this:
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_Bool f(_Bool a) { return a!=1; }
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into:
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movzbl %dil, %eax
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xorl $1, %eax
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ret
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//===---------------------------------------------------------------------===//
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Some isel ideas:
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1. Dynamic programming based approach when compile time if not an
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issue.
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2. Code duplication (addressing mode) during isel.
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3. Other ideas from "Register-Sensitive Selection, Duplication, and
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Sequencing of Instructions".
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//===---------------------------------------------------------------------===//
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Should we promote i16 to i32 to avoid partial register update stalls?
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//===---------------------------------------------------------------------===//
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Leave any_extend as pseudo instruction and hint to register
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allocator. Delay codegen until post register allocation.
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