Alex Bradbury 920aa533c1 [RISCV] Add missing hunk from r316188 ... r316188 didn't set guessInstructionProperties=1 as it should have done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316189 91177308-0d34-0410-b5e6-96231b3b80d8		2017-10-19 21:43:29 +00:00
..
AsmParser	[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected	2017-10-19 16:22:51 +00:00
Disassembler	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
InstPrinter	[RISCV] Add support for all RV32I instructions	2017-09-17 14:27:35 +00:00
MCTargetDesc	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
TargetInfo
CMakeLists.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
LLVMBuild.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.td	[RISCV] Add missing hunk from r316188	2017-10-19 21:43:29 +00:00
RISCVAsmPrinter.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVCallingConv.td	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVFrameLowering.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVFrameLowering.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVInstrFormats.td	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
RISCVInstrInfo.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVInstrInfo.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVInstrInfo.td	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVISelLowering.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVISelLowering.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVMCInstLower.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVRegisterInfo.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVRegisterInfo.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVRegisterInfo.td	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetMachine.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00