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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
1.3 KiB
LLVM
32 lines
1.3 KiB
LLVM
; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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; We will keep trying to vectorize the basic block even we already find vectorized store.
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; CHECK: test1
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; CHECK: store <2 x double>
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; CHECK: ret
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define void @test1(double* %a, double* %b, double* %c, double* %d) {
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entry:
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%i0 = load double, double* %a, align 8
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%i1 = load double, double* %b, align 8
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%mul = fmul double %i0, %i1
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%arrayidx3 = getelementptr inbounds double, double* %a, i64 1
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%i3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %b, i64 1
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%i4 = load double, double* %arrayidx4, align 8
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%mul5 = fmul double %i3, %i4
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store double %mul, double* %c, align 8
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%arrayidx5 = getelementptr inbounds double, double* %c, i64 1
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store double %mul5, double* %arrayidx5, align 8
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%0 = bitcast double* %a to <4 x i32>*
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%1 = load <4 x i32>, <4 x i32>* %0, align 8
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%2 = bitcast double* %b to <4 x i32>*
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%3 = load <4 x i32>, <4 x i32>* %2, align 8
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%4 = mul <4 x i32> %1, %3
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%5 = bitcast double* %d to <4 x i32>*
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store <4 x i32> %4, <4 x i32>* %5, align 8
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ret void
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}
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