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a816f42e4d
I don't know how to expose this in a test. There are ARM / AArch64 sched classes that include zero latency instructions, but I'm not seeing sched info printed for those targets. X86 will almost certainly have these soon (see PR36671), but no model has 'let Latency = 0' currently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327518 91177308-0d34-0410-b5e6-96231b3b80d8
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