llvm/R600 at a92f8ee2f3ee12d26f6ed0720c763021cfa22ca8 - llvm - Gitea: Git with a cup of tea

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-01-21 09:25:07 +00:00

History

Vincent Lejeune a92f8ee2f3 R600: Don't mix LDS and non-LDS instructions in the same group

There are a lot of restrictions on instruction groups that contain
LDS instructions, so for now we will be conservative and not packetize
anything else with them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513 91177308-0d34-0410-b5e6-96231b3b80d8

2013-07-31 19:31:41 +00:00

..

R600: Bank Swizzle now display SCL equivalent

2013-06-29 19:32:29 +00:00

Remove address spaces from MC.

2013-07-02 15:49:13 +00:00

R600: Remove unnecessary include

2013-06-07 20:28:43 +00:00

AMDGPU.h

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDGPU.td

R600: Rework subtarget info and remove AMDILDevice classes

2013-06-07 20:37:48 +00:00

AMDGPUAsmPrinter.cpp

R600/SI: Initial local memory support

2013-07-10 16:37:07 +00:00

AMDGPUAsmPrinter.h

…

AMDGPUCallingConv.td

R600: Use the same compute kernel calling convention for all GPUs

2013-07-23 01:48:05 +00:00

AMDGPUConvertToISA.cpp

…

AMDGPUFrameLowering.cpp

R600: Fix calculation of stack offset in AMDGPUFrameLowering

2013-06-07 20:52:05 +00:00

AMDGPUFrameLowering.h

…

AMDGPUIndirectAddressing.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

AMDGPUInstrInfo.cpp

R600: Use new getNamedOperandIdx function generated by TableGen

2013-06-25 21:22:18 +00:00

AMDGPUInstrInfo.h

R600: Use new getNamedOperandIdx function generated by TableGen

2013-06-25 21:22:18 +00:00

AMDGPUInstrInfo.td

…

AMDGPUInstructions.td

R600: Add support for 24-bit MUL instructions

2013-07-23 01:48:42 +00:00

AMDGPUIntrinsics.td

R600: Add support for GROUP_BARRIER instruction

2013-06-28 15:46:59 +00:00

AMDGPUISelDAGToDAG.cpp

R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary

2013-07-23 23:54:56 +00:00

AMDGPUISelLowering.cpp

R600/SI: Expand vector fp <-> int conversions

2013-07-30 14:31:03 +00:00

AMDGPUISelLowering.h

DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free

2013-07-23 23:55:03 +00:00

AMDGPUMachineFunction.cpp

Move string pointer from being a static class member to just a static global in the one file its needed in.

2013-07-17 00:31:35 +00:00

AMDGPUMachineFunction.h

Move string pointer from being a static class member to just a static global in the one file its needed in.

2013-07-17 00:31:35 +00:00

AMDGPUMCInstLower.cpp

…

AMDGPUMCInstLower.h

…

AMDGPURegisterInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

AMDGPURegisterInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

AMDGPURegisterInfo.td

…

AMDGPUSubtarget.cpp

R600: Rework subtarget info and remove AMDILDevice classes

2013-06-07 20:37:48 +00:00

AMDGPUSubtarget.h

R600: Rework subtarget info and remove AMDILDevice classes

2013-06-07 20:37:48 +00:00

AMDGPUTargetMachine.cpp

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDGPUTargetMachine.h

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDGPUTargetTransformInfo.cpp

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDILBase.td

R600: Move Subtarget feature definitions into AMDGPU.td

2013-06-07 20:28:49 +00:00

AMDILCFGStructurizer.cpp

R600: Remove predicated_break inst

2013-07-31 19:31:14 +00:00

AMDILInstrInfo.td

R600: Rework subtarget info and remove AMDILDevice classes

2013-06-07 20:37:48 +00:00

AMDILIntrinsicInfo.cpp

R600: Rework subtarget info and remove AMDILDevice classes

2013-06-07 20:37:48 +00:00

AMDILIntrinsicInfo.h

…

AMDILIntrinsics.td

…

AMDILISelLowering.cpp

Make some arrays 'static const'

2013-07-15 06:39:13 +00:00

AMDILRegisterInfo.td

…

CMakeLists.txt

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

LLVMBuild.txt

…

Makefile

…

Processors.td

Add a newline.

2013-07-01 21:31:10 +00:00

R600ControlFlowFinalizer.cpp

R600: Remove predicated_break inst

2013-07-31 19:31:14 +00:00

R600Defines.h

R600: Add local memory support via LDS

2013-06-28 15:47:08 +00:00

R600EmitClauseMarkers.cpp

Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.

2013-07-14 04:42:23 +00:00

R600ExpandSpecialInstrs.cpp

R600: Remove predicated_break inst

2013-07-31 19:31:14 +00:00

R600InstrFormats.td

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-07-31 19:31:35 +00:00

R600InstrInfo.cpp

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-07-31 19:31:35 +00:00

R600InstrInfo.h

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-07-31 19:31:35 +00:00

R600Instructions.td

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-07-31 19:31:35 +00:00

R600Intrinsics.td

…

R600ISelLowering.cpp

R600/SI: Expand vector fp <-> int conversions

2013-07-30 14:31:03 +00:00

R600ISelLowering.h

R600: Use DAG lowering pass to handle fcos/fsin

2013-07-09 15:03:11 +00:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

R600: Support schedule and packetization of trans-only inst

2013-06-29 19:32:43 +00:00

R600MachineScheduler.h

R600: Support schedule and packetization of trans-only inst

2013-06-29 19:32:43 +00:00

R600OptimizeVectorRegisters.cpp

R600: Fix wrong export reswizzling

2013-07-09 15:03:19 +00:00

R600Packetizer.cpp

R600: Don't mix LDS and non-LDS instructions in the same group

2013-07-31 19:31:41 +00:00

R600RegisterInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

R600RegisterInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

R600RegisterInfo.td

R600: Simplify assembly for KCache registers using the TableGen !add operator

2013-07-23 01:48:08 +00:00

R600Schedule.td

R600: Add local memory support via LDS

2013-06-28 15:47:08 +00:00

R600TextureIntrinsicsReplacer.cpp

…

SIAnnotateControlFlow.cpp

Add 'const' qualifiers to static const char* variables.

2013-07-16 01:17:10 +00:00

SIDefines.h

R600/SI: Initial local memory support

2013-07-10 16:37:07 +00:00

SIInsertWaits.cpp

R600/SI: Initial support for LDS/GDS instructions

2013-07-10 16:36:43 +00:00

SIInstrFormats.td

R600/SI: Initial support for LDS/GDS instructions

2013-07-10 16:36:43 +00:00

SIInstrInfo.cpp

Make some arrays 'static const'

2013-07-15 06:39:13 +00:00

SIInstrInfo.h

…

SIInstrInfo.td

R600: Remove unsafe type punning. No intended functionality change.

2013-07-12 20:18:05 +00:00

SIInstructions.td

R600: Add support for 24-bit MAD instructions

2013-07-23 01:48:49 +00:00

SIIntrinsics.td

R600/SI: Add intrinsic for retrieving the current thread ID

2013-07-10 16:36:52 +00:00

SIISelLowering.cpp

R600: Improve support for < 32-bit loads

2013-07-23 01:48:35 +00:00

SIISelLowering.h

R600/SI: Report unaligned memory accesses as legal for > 32-bit types

2013-06-25 02:39:35 +00:00

SILowerControlFlow.cpp

R600/SI: Initial support for LDS/GDS instructions

2013-07-10 16:36:43 +00:00

SIMachineFunctionInfo.cpp

…

SIMachineFunctionInfo.h

…

SIRegisterInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

SIRegisterInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 20:28:55 +00:00

SIRegisterInfo.td

R600/SI: Add support for v2f32 loads

2013-07-18 21:43:48 +00:00

SISchedule.td

…