mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-28 14:10:55 +00:00
fd5a8723ce
Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typical workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323155 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
7.9 KiB
C++
222 lines
7.9 KiB
C++
//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
/// \file
|
|
///
|
|
/// Implements an expansion pass to turn `indirectbr` instructions in the IR
|
|
/// into `switch` instructions. This works by enumerating the basic blocks in
|
|
/// a dense range of integers, replacing each `blockaddr` constant with the
|
|
/// corresponding integer constant, and then building a switch that maps from
|
|
/// the integers to the actual blocks. All of the indirectbr instructions in the
|
|
/// function are redirected to this common switch.
|
|
///
|
|
/// While this is generically useful if a target is unable to codegen
|
|
/// `indirectbr` natively, it is primarily useful when there is some desire to
|
|
/// get the builtin non-jump-table lowering of a switch even when the input
|
|
/// source contained an explicit indirect branch construct.
|
|
///
|
|
/// Note that it doesn't make any sense to enable this pass unless a target also
|
|
/// disables jump-table lowering of switches. Doing that is likely to pessimize
|
|
/// the code.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/ADT/Sequence.h"
|
|
#include "llvm/ADT/SmallVector.h"
|
|
#include "llvm/CodeGen/TargetPassConfig.h"
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
|
#include "llvm/IR/BasicBlock.h"
|
|
#include "llvm/IR/Function.h"
|
|
#include "llvm/IR/IRBuilder.h"
|
|
#include "llvm/IR/InstIterator.h"
|
|
#include "llvm/IR/Instruction.h"
|
|
#include "llvm/IR/Instructions.h"
|
|
#include "llvm/Pass.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "indirectbr-expand"
|
|
|
|
namespace {
|
|
|
|
class IndirectBrExpandPass : public FunctionPass {
|
|
const TargetLowering *TLI = nullptr;
|
|
|
|
public:
|
|
static char ID; // Pass identification, replacement for typeid
|
|
|
|
IndirectBrExpandPass() : FunctionPass(ID) {
|
|
initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry());
|
|
}
|
|
|
|
bool runOnFunction(Function &F) override;
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
char IndirectBrExpandPass::ID = 0;
|
|
|
|
INITIALIZE_PASS(IndirectBrExpandPass, DEBUG_TYPE,
|
|
"Expand indirectbr instructions", false, false)
|
|
|
|
FunctionPass *llvm::createIndirectBrExpandPass() {
|
|
return new IndirectBrExpandPass();
|
|
}
|
|
|
|
bool IndirectBrExpandPass::runOnFunction(Function &F) {
|
|
auto &DL = F.getParent()->getDataLayout();
|
|
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
|
|
if (!TPC)
|
|
return false;
|
|
|
|
auto &TM = TPC->getTM<TargetMachine>();
|
|
auto &STI = *TM.getSubtargetImpl(F);
|
|
if (!STI.enableIndirectBrExpand())
|
|
return false;
|
|
TLI = STI.getTargetLowering();
|
|
|
|
SmallVector<IndirectBrInst *, 1> IndirectBrs;
|
|
|
|
// Set of all potential successors for indirectbr instructions.
|
|
SmallPtrSet<BasicBlock *, 4> IndirectBrSuccs;
|
|
|
|
// Build a list of indirectbrs that we want to rewrite.
|
|
for (BasicBlock &BB : F)
|
|
if (auto *IBr = dyn_cast<IndirectBrInst>(BB.getTerminator())) {
|
|
// Handle the degenerate case of no successors by replacing the indirectbr
|
|
// with unreachable as there is no successor available.
|
|
if (IBr->getNumSuccessors() == 0) {
|
|
(void)new UnreachableInst(F.getContext(), IBr);
|
|
IBr->eraseFromParent();
|
|
continue;
|
|
}
|
|
|
|
IndirectBrs.push_back(IBr);
|
|
for (BasicBlock *SuccBB : IBr->successors())
|
|
IndirectBrSuccs.insert(SuccBB);
|
|
}
|
|
|
|
if (IndirectBrs.empty())
|
|
return false;
|
|
|
|
// If we need to replace any indirectbrs we need to establish integer
|
|
// constants that will correspond to each of the basic blocks in the function
|
|
// whose address escapes. We do that here and rewrite all the blockaddress
|
|
// constants to just be those integer constants cast to a pointer type.
|
|
SmallVector<BasicBlock *, 4> BBs;
|
|
|
|
for (BasicBlock &BB : F) {
|
|
// Skip blocks that aren't successors to an indirectbr we're going to
|
|
// rewrite.
|
|
if (!IndirectBrSuccs.count(&BB))
|
|
continue;
|
|
|
|
auto IsBlockAddressUse = [&](const Use &U) {
|
|
return isa<BlockAddress>(U.getUser());
|
|
};
|
|
auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse);
|
|
if (BlockAddressUseIt == BB.use_end())
|
|
continue;
|
|
|
|
assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(),
|
|
IsBlockAddressUse) == BB.use_end() &&
|
|
"There should only ever be a single blockaddress use because it is "
|
|
"a constant and should be uniqued.");
|
|
|
|
auto *BA = cast<BlockAddress>(BlockAddressUseIt->getUser());
|
|
|
|
// Skip if the constant was formed but ended up not being used (due to DCE
|
|
// or whatever).
|
|
if (!BA->isConstantUsed())
|
|
continue;
|
|
|
|
// Compute the index we want to use for this basic block. We can't use zero
|
|
// because null can be compared with block addresses.
|
|
int BBIndex = BBs.size() + 1;
|
|
BBs.push_back(&BB);
|
|
|
|
auto *ITy = cast<IntegerType>(DL.getIntPtrType(BA->getType()));
|
|
ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex);
|
|
|
|
// Now rewrite the blockaddress to an integer constant based on the index.
|
|
// FIXME: We could potentially preserve the uses as arguments to inline asm.
|
|
// This would allow some uses such as diagnostic information in crashes to
|
|
// have higher quality even when this transform is enabled, but would break
|
|
// users that round-trip blockaddresses through inline assembly and then
|
|
// back into an indirectbr.
|
|
BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType()));
|
|
}
|
|
|
|
if (BBs.empty()) {
|
|
// There are no blocks whose address is taken, so any indirectbr instruction
|
|
// cannot get a valid input and we can replace all of them with unreachable.
|
|
for (auto *IBr : IndirectBrs) {
|
|
(void)new UnreachableInst(F.getContext(), IBr);
|
|
IBr->eraseFromParent();
|
|
}
|
|
return true;
|
|
}
|
|
|
|
BasicBlock *SwitchBB;
|
|
Value *SwitchValue;
|
|
|
|
// Compute a common integer type across all the indirectbr instructions.
|
|
IntegerType *CommonITy = nullptr;
|
|
for (auto *IBr : IndirectBrs) {
|
|
auto *ITy =
|
|
cast<IntegerType>(DL.getIntPtrType(IBr->getAddress()->getType()));
|
|
if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth())
|
|
CommonITy = ITy;
|
|
}
|
|
|
|
auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) {
|
|
return CastInst::CreatePointerCast(
|
|
IBr->getAddress(), CommonITy,
|
|
Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr);
|
|
};
|
|
|
|
if (IndirectBrs.size() == 1) {
|
|
// If we only have one indirectbr, we can just directly replace it within
|
|
// its block.
|
|
SwitchBB = IndirectBrs[0]->getParent();
|
|
SwitchValue = GetSwitchValue(IndirectBrs[0]);
|
|
IndirectBrs[0]->eraseFromParent();
|
|
} else {
|
|
// Otherwise we need to create a new block to hold the switch across BBs,
|
|
// jump to that block instead of each indirectbr, and phi together the
|
|
// values for the switch.
|
|
SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F);
|
|
auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(),
|
|
"switch_value_phi", SwitchBB);
|
|
SwitchValue = SwitchPN;
|
|
|
|
// Now replace the indirectbr instructions with direct branches to the
|
|
// switch block and fill out the PHI operands.
|
|
for (auto *IBr : IndirectBrs) {
|
|
SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent());
|
|
BranchInst::Create(SwitchBB, IBr);
|
|
IBr->eraseFromParent();
|
|
}
|
|
}
|
|
|
|
// Now build the switch in the block. The block will have no terminator
|
|
// already.
|
|
auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB);
|
|
|
|
// Add a case for each block.
|
|
for (int i : llvm::seq<int>(1, BBs.size()))
|
|
SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]);
|
|
|
|
return true;
|
|
}
|