mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-24 20:30:06 +00:00
af56683019
Summary:
This pass sinks COPY instructions into a successor block, if the COPY is not
used in the current block and the COPY is live-in to a single successor
(i.e., doesn't require the COPY to be duplicated). This avoids executing the
the copy on paths where their results aren't needed. This also exposes
additional opportunites for dead copy elimination and shrink wrapping.
These copies were either not handled by or are inserted after the MachineSink
pass. As an example of the former case, the MachineSink pass cannot sink
COPY instructions with allocatable source registers; for AArch64 these type
of copy instructions are frequently used to move function parameters (PhyReg)
into virtual registers in the entry block..
For the machine IR below, this pass will sink %w19 in the entry into its
successor (%bb.1) because %w19 is only live-in in %bb.1.
```
%bb.0:
%wzr = SUBSWri %w1, 1
%w19 = COPY %w0
Bcc 11, %bb.2
%bb.1:
Live Ins: %w19
BL @fun
%w0 = ADDWrr %w0, %w19
RET %w0
%bb.2:
%w0 = COPY %wzr
RET %w0
```
As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
able to see %bb.0 as a candidate.
With this change I observed 12% more shrink-wrapping candidate and 13% more dead copies deleted in spec2000/2006/2017 on AArch64.
Reviewers: qcolombet, MatzeB, thegameg, mcrosier, gberry, hfinkel, john.brawn, twoh, RKSimon, sebpop, kparzysz
Reviewed By: sebpop
Subscribers: evandro, sebpop, sfertile, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328237 91177308-0d34-0410-b5e6-96231b3b80d8
1259 lines
47 KiB
C++
1259 lines
47 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cctype>
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using namespace llvm;
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static cl::opt<bool> DisableHazardRecognizer(
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"disable-sched-hazard", cl::Hidden, cl::init(false),
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cl::desc("Disable hazard detection during preRA scheduling"));
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TargetInstrInfo::~TargetInstrInfo() {
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}
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const TargetRegisterClass*
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TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
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const TargetRegisterInfo *TRI,
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const MachineFunction &MF) const {
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if (OpNum >= MCID.getNumOperands())
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return nullptr;
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short RegClass = MCID.OpInfo[OpNum].RegClass;
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if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
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return TRI->getPointerRegClass(MF, RegClass);
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// Instructions like INSERT_SUBREG do not have fixed register classes.
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if (RegClass < 0)
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return nullptr;
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// Otherwise just look it up normally.
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return TRI->getRegClass(RegClass);
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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llvm_unreachable("Target didn't implement insertNoop!");
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}
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static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) {
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return strncmp(Str, MAI.getCommentString().data(),
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MAI.getCommentString().size()) == 0;
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}
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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/// Comments (which run till the next SeparatorString or newline) do not
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/// count as an instruction.
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/// Any other non-whitespace text is considered an instruction, with
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/// multiple instructions separated by SeparatorString or newlines.
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/// Variable-length instructions are not handled here; this function
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/// may be overloaded in the target code to do that.
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/// We implement a special case of the .space directive which takes only a
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/// single integer argument in base 10 that is the size in bytes. This is a
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/// restricted form of the GAS directive in that we only interpret
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/// simple--i.e. not a logical or arithmetic expression--size values without
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/// the optional fill value. This is primarily used for creating arbitrary
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/// sized inline asm blocks for testing purposes.
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unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const {
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// Count the number of instructions in the asm.
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bool AtInsnStart = true;
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unsigned Length = 0;
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for (; *Str; ++Str) {
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if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
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strlen(MAI.getSeparatorString())) == 0) {
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AtInsnStart = true;
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} else if (isAsmComment(Str, MAI)) {
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// Stop counting as an instruction after a comment until the next
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// separator.
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AtInsnStart = false;
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}
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if (AtInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
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unsigned AddLength = MAI.getMaxInstLength();
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if (strncmp(Str, ".space", 6) == 0) {
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char *EStr;
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int SpaceSize;
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SpaceSize = strtol(Str + 6, &EStr, 10);
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SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;
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while (*EStr != '\n' && std::isspace(static_cast<unsigned char>(*EStr)))
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++EStr;
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if (*EStr == '\0' || *EStr == '\n' ||
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isAsmComment(EStr, MAI)) // Successfully parsed .space argument
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AddLength = SpaceSize;
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}
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Length += AddLength;
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AtInsnStart = false;
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}
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}
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return Length;
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}
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/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
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/// after it, replacing it with an unconditional branch to NewDest.
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void
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TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const {
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MachineBasicBlock *MBB = Tail->getParent();
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// Remove all the old successors of MBB from the CFG.
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while (!MBB->succ_empty())
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MBB->removeSuccessor(MBB->succ_begin());
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// Save off the debug loc before erasing the instruction.
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DebugLoc DL = Tail->getDebugLoc();
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// Remove all the dead instructions from the end of MBB.
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MBB->erase(Tail, MBB->end());
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// If MBB isn't immediately before MBB, insert a branch to it.
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if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
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insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
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MBB->addSuccessor(NewDest);
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}
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MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
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bool NewMI, unsigned Idx1,
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unsigned Idx2) const {
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const MCInstrDesc &MCID = MI.getDesc();
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bool HasDef = MCID.getNumDefs();
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if (HasDef && !MI.getOperand(0).isReg())
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// No idea how to commute this instruction. Target should implement its own.
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return nullptr;
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unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
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unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
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assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
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CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
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"TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
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assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
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"This only knows how to commute register operands so far");
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unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
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unsigned Reg1 = MI.getOperand(Idx1).getReg();
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unsigned Reg2 = MI.getOperand(Idx2).getReg();
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unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
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unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
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unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
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bool Reg1IsKill = MI.getOperand(Idx1).isKill();
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bool Reg2IsKill = MI.getOperand(Idx2).isKill();
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bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
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bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
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bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
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bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
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// Avoid calling isRenamable for virtual registers since we assert that
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// renamable property is only queried/set for physical registers.
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bool Reg1IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg1)
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? MI.getOperand(Idx1).isRenamable()
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: false;
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bool Reg2IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg2)
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? MI.getOperand(Idx2).isRenamable()
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: false;
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// If destination is tied to either of the commuted source register, then
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// it must be updated.
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if (HasDef && Reg0 == Reg1 &&
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MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
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Reg2IsKill = false;
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Reg0 = Reg2;
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SubReg0 = SubReg2;
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} else if (HasDef && Reg0 == Reg2 &&
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MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
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Reg1IsKill = false;
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Reg0 = Reg1;
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SubReg0 = SubReg1;
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}
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MachineInstr *CommutedMI = nullptr;
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if (NewMI) {
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// Create a new instruction.
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MachineFunction &MF = *MI.getMF();
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CommutedMI = MF.CloneMachineInstr(&MI);
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} else {
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CommutedMI = &MI;
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}
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if (HasDef) {
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CommutedMI->getOperand(0).setReg(Reg0);
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CommutedMI->getOperand(0).setSubReg(SubReg0);
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}
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CommutedMI->getOperand(Idx2).setReg(Reg1);
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CommutedMI->getOperand(Idx1).setReg(Reg2);
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CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
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CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
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CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
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CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
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CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
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CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
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CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
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CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
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// Avoid calling setIsRenamable for virtual registers since we assert that
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// renamable property is only queried/set for physical registers.
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if (TargetRegisterInfo::isPhysicalRegister(Reg1))
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CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
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if (TargetRegisterInfo::isPhysicalRegister(Reg2))
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CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
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return CommutedMI;
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}
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MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const {
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// If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
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// any commutable operand, which is done in findCommutedOpIndices() method
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// called below.
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if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
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!findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
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assert(MI.isCommutable() &&
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"Precondition violation: MI must be commutable.");
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return nullptr;
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}
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return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
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unsigned &ResultIdx2,
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unsigned CommutableOpIdx1,
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unsigned CommutableOpIdx2) {
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if (ResultIdx1 == CommuteAnyOperandIndex &&
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ResultIdx2 == CommuteAnyOperandIndex) {
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ResultIdx1 = CommutableOpIdx1;
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ResultIdx2 = CommutableOpIdx2;
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} else if (ResultIdx1 == CommuteAnyOperandIndex) {
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if (ResultIdx2 == CommutableOpIdx1)
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ResultIdx1 = CommutableOpIdx2;
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else if (ResultIdx2 == CommutableOpIdx2)
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ResultIdx1 = CommutableOpIdx1;
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else
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return false;
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} else if (ResultIdx2 == CommuteAnyOperandIndex) {
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if (ResultIdx1 == CommutableOpIdx1)
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ResultIdx2 = CommutableOpIdx2;
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else if (ResultIdx1 == CommutableOpIdx2)
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ResultIdx2 = CommutableOpIdx1;
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else
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return false;
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} else
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// Check that the result operand indices match the given commutable
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// operand indices.
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return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
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(ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
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return true;
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}
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bool TargetInstrInfo::findCommutedOpIndices(MachineInstr &MI,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const {
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assert(!MI.isBundle() &&
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"TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
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const MCInstrDesc &MCID = MI.getDesc();
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if (!MCID.isCommutable())
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return false;
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// This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
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// is not true, then the target must implement this.
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unsigned CommutableOpIdx1 = MCID.getNumDefs();
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unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
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if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
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CommutableOpIdx1, CommutableOpIdx2))
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return false;
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if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
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// No idea.
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return false;
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return true;
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}
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bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
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if (!MI.isTerminator()) return false;
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// Conditional branch is a special case.
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if (MI.isBranch() && !MI.isBarrier())
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return true;
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if (!MI.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool TargetInstrInfo::PredicateInstruction(
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MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
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bool MadeChange = false;
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assert(!MI.isBundle() &&
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"TargetInstrInfo::PredicateInstruction() can't handle bundles");
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const MCInstrDesc &MCID = MI.getDesc();
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if (!MI.isPredicable())
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return false;
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for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (MCID.OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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return MadeChange;
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}
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bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
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oe = MI.memoperands_end();
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o != oe; ++o) {
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if ((*o)->isLoad()) {
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast_or_null<FixedStackPseudoSourceValue>(
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(*o)->getPseudoValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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}
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}
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return false;
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}
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bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
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oe = MI.memoperands_end();
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o != oe; ++o) {
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if ((*o)->isStore()) {
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast_or_null<FixedStackPseudoSourceValue>(
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(*o)->getPseudoValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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}
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}
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return false;
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}
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bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
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unsigned SubIdx, unsigned &Size,
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unsigned &Offset,
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const MachineFunction &MF) const {
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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if (!SubIdx) {
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Size = TRI->getSpillSize(*RC);
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Offset = 0;
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return true;
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}
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unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
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// Convert bit size to byte size to be consistent with
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// MCRegisterClass::getSize().
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if (BitSize % 8)
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return false;
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int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
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if (BitOffset < 0 || BitOffset % 8)
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return false;
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Size = BitSize /= 8;
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Offset = (unsigned)BitOffset / 8;
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assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
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if (!MF.getDataLayout().isLittleEndian()) {
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Offset = TRI->getSpillSize(*RC) - (Offset + Size);
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}
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return true;
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}
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void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr &Orig,
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const TargetRegisterInfo &TRI) const {
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
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MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
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MBB.insert(I, MI);
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}
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bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
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const MachineInstr &MI1,
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const MachineRegisterInfo *MRI) const {
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return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
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}
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MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
|
|
assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
|
|
MachineFunction &MF = *MBB.getParent();
|
|
return MF.CloneMachineInstrBundle(MBB, InsertBefore, Orig);
|
|
}
|
|
|
|
// If the COPY instruction in MI can be folded to a stack operation, return
|
|
// the register class to use.
|
|
static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
|
|
unsigned FoldIdx) {
|
|
assert(MI.isCopy() && "MI must be a COPY instruction");
|
|
if (MI.getNumOperands() != 2)
|
|
return nullptr;
|
|
assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
|
|
|
|
const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
|
|
const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
|
|
|
|
if (FoldOp.getSubReg() || LiveOp.getSubReg())
|
|
return nullptr;
|
|
|
|
unsigned FoldReg = FoldOp.getReg();
|
|
unsigned LiveReg = LiveOp.getReg();
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
|
|
"Cannot fold physregs");
|
|
|
|
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
|
|
const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
|
|
return RC->contains(LiveOp.getReg()) ? RC : nullptr;
|
|
|
|
if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
|
|
return RC;
|
|
|
|
// FIXME: Allow folding when register classes are memory compatible.
|
|
return nullptr;
|
|
}
|
|
|
|
void TargetInstrInfo::getNoop(MCInst &NopInst) const {
|
|
llvm_unreachable("Not implemented");
|
|
}
|
|
|
|
static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
|
|
ArrayRef<unsigned> Ops, int FrameIndex,
|
|
const TargetInstrInfo &TII) {
|
|
unsigned StartIdx = 0;
|
|
switch (MI.getOpcode()) {
|
|
case TargetOpcode::STACKMAP: {
|
|
// StackMapLiveValues are foldable
|
|
StartIdx = StackMapOpers(&MI).getVarIdx();
|
|
break;
|
|
}
|
|
case TargetOpcode::PATCHPOINT: {
|
|
// For PatchPoint, the call args are not foldable (even if reported in the
|
|
// stackmap e.g. via anyregcc).
|
|
StartIdx = PatchPointOpers(&MI).getVarIdx();
|
|
break;
|
|
}
|
|
case TargetOpcode::STATEPOINT: {
|
|
// For statepoints, fold deopt and gc arguments, but not call arguments.
|
|
StartIdx = StatepointOpers(&MI).getVarIdx();
|
|
break;
|
|
}
|
|
default:
|
|
llvm_unreachable("unexpected stackmap opcode");
|
|
}
|
|
|
|
// Return false if any operands requested for folding are not foldable (not
|
|
// part of the stackmap's live values).
|
|
for (unsigned Op : Ops) {
|
|
if (Op < StartIdx)
|
|
return nullptr;
|
|
}
|
|
|
|
MachineInstr *NewMI =
|
|
MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
|
|
MachineInstrBuilder MIB(MF, NewMI);
|
|
|
|
// No need to fold return, the meta data, and function arguments
|
|
for (unsigned i = 0; i < StartIdx; ++i)
|
|
MIB.add(MI.getOperand(i));
|
|
|
|
for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) {
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
if (is_contained(Ops, i)) {
|
|
unsigned SpillSize;
|
|
unsigned SpillOffset;
|
|
// Compute the spill slot size and offset.
|
|
const TargetRegisterClass *RC =
|
|
MF.getRegInfo().getRegClass(MO.getReg());
|
|
bool Valid =
|
|
TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
|
|
if (!Valid)
|
|
report_fatal_error("cannot spill patchpoint subregister operand");
|
|
MIB.addImm(StackMaps::IndirectMemRefOp);
|
|
MIB.addImm(SpillSize);
|
|
MIB.addFrameIndex(FrameIndex);
|
|
MIB.addImm(SpillOffset);
|
|
}
|
|
else
|
|
MIB.add(MO);
|
|
}
|
|
return NewMI;
|
|
}
|
|
|
|
MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
|
|
ArrayRef<unsigned> Ops, int FI,
|
|
LiveIntervals *LIS) const {
|
|
auto Flags = MachineMemOperand::MONone;
|
|
for (unsigned OpIdx : Ops)
|
|
Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
|
|
: MachineMemOperand::MOLoad;
|
|
|
|
MachineBasicBlock *MBB = MI.getParent();
|
|
assert(MBB && "foldMemoryOperand needs an inserted instruction");
|
|
MachineFunction &MF = *MBB->getParent();
|
|
|
|
// If we're not folding a load into a subreg, the size of the load is the
|
|
// size of the spill slot. But if we are, we need to figure out what the
|
|
// actual load size is.
|
|
int64_t MemSize = 0;
|
|
const MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
|
|
if (Flags & MachineMemOperand::MOStore) {
|
|
MemSize = MFI.getObjectSize(FI);
|
|
} else {
|
|
for (unsigned OpIdx : Ops) {
|
|
int64_t OpSize = MFI.getObjectSize(FI);
|
|
|
|
if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
|
|
unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
|
|
if (SubRegSize > 0 && !(SubRegSize % 8))
|
|
OpSize = SubRegSize / 8;
|
|
}
|
|
|
|
MemSize = std::max(MemSize, OpSize);
|
|
}
|
|
}
|
|
|
|
assert(MemSize && "Did not expect a zero-sized stack slot");
|
|
|
|
MachineInstr *NewMI = nullptr;
|
|
|
|
if (MI.getOpcode() == TargetOpcode::STACKMAP ||
|
|
MI.getOpcode() == TargetOpcode::PATCHPOINT ||
|
|
MI.getOpcode() == TargetOpcode::STATEPOINT) {
|
|
// Fold stackmap/patchpoint.
|
|
NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
|
|
if (NewMI)
|
|
MBB->insert(MI, NewMI);
|
|
} else {
|
|
// Ask the target to do the actual folding.
|
|
NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS);
|
|
}
|
|
|
|
if (NewMI) {
|
|
NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
|
|
// Add a memory operand, foldMemoryOperandImpl doesn't do that.
|
|
assert((!(Flags & MachineMemOperand::MOStore) ||
|
|
NewMI->mayStore()) &&
|
|
"Folded a def to a non-store!");
|
|
assert((!(Flags & MachineMemOperand::MOLoad) ||
|
|
NewMI->mayLoad()) &&
|
|
"Folded a use to a non-load!");
|
|
assert(MFI.getObjectOffset(FI) != -1);
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(MF, FI), Flags, MemSize,
|
|
MFI.getObjectAlignment(FI));
|
|
NewMI->addMemOperand(MF, MMO);
|
|
|
|
return NewMI;
|
|
}
|
|
|
|
// Straight COPY may fold as load/store.
|
|
if (!MI.isCopy() || Ops.size() != 1)
|
|
return nullptr;
|
|
|
|
const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
|
|
if (!RC)
|
|
return nullptr;
|
|
|
|
const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
|
|
MachineBasicBlock::iterator Pos = MI;
|
|
|
|
if (Flags == MachineMemOperand::MOStore)
|
|
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
|
|
else
|
|
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
|
|
return &*--Pos;
|
|
}
|
|
|
|
MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
|
|
ArrayRef<unsigned> Ops,
|
|
MachineInstr &LoadMI,
|
|
LiveIntervals *LIS) const {
|
|
assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
|
|
#ifndef NDEBUG
|
|
for (unsigned OpIdx : Ops)
|
|
assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
|
|
#endif
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
// Ask the target to do the actual folding.
|
|
MachineInstr *NewMI = nullptr;
|
|
int FrameIndex = 0;
|
|
|
|
if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
|
|
MI.getOpcode() == TargetOpcode::PATCHPOINT ||
|
|
MI.getOpcode() == TargetOpcode::STATEPOINT) &&
|
|
isLoadFromStackSlot(LoadMI, FrameIndex)) {
|
|
// Fold stackmap/patchpoint.
|
|
NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
|
|
if (NewMI)
|
|
NewMI = &*MBB.insert(MI, NewMI);
|
|
} else {
|
|
// Ask the target to do the actual folding.
|
|
NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
|
|
}
|
|
|
|
if (!NewMI)
|
|
return nullptr;
|
|
|
|
// Copy the memoperands from the load to the folded instruction.
|
|
if (MI.memoperands_empty()) {
|
|
NewMI->setMemRefs(LoadMI.memoperands_begin(), LoadMI.memoperands_end());
|
|
} else {
|
|
// Handle the rare case of folding multiple loads.
|
|
NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
|
|
for (MachineInstr::mmo_iterator I = LoadMI.memoperands_begin(),
|
|
E = LoadMI.memoperands_end();
|
|
I != E; ++I) {
|
|
NewMI->addMemOperand(MF, *I);
|
|
}
|
|
}
|
|
return NewMI;
|
|
}
|
|
|
|
bool TargetInstrInfo::hasReassociableOperands(
|
|
const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
|
|
const MachineOperand &Op1 = Inst.getOperand(1);
|
|
const MachineOperand &Op2 = Inst.getOperand(2);
|
|
const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
|
|
|
// We need virtual register definitions for the operands that we will
|
|
// reassociate.
|
|
MachineInstr *MI1 = nullptr;
|
|
MachineInstr *MI2 = nullptr;
|
|
if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
|
|
MI1 = MRI.getUniqueVRegDef(Op1.getReg());
|
|
if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
|
|
MI2 = MRI.getUniqueVRegDef(Op2.getReg());
|
|
|
|
// And they need to be in the trace (otherwise, they won't have a depth).
|
|
return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
|
|
}
|
|
|
|
bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
|
|
bool &Commuted) const {
|
|
const MachineBasicBlock *MBB = Inst.getParent();
|
|
const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
|
MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
|
|
MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
|
|
unsigned AssocOpcode = Inst.getOpcode();
|
|
|
|
// If only one operand has the same opcode and it's the second source operand,
|
|
// the operands must be commuted.
|
|
Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
|
|
if (Commuted)
|
|
std::swap(MI1, MI2);
|
|
|
|
// 1. The previous instruction must be the same type as Inst.
|
|
// 2. The previous instruction must have virtual register definitions for its
|
|
// operands in the same basic block as Inst.
|
|
// 3. The previous instruction's result must only be used by Inst.
|
|
return MI1->getOpcode() == AssocOpcode &&
|
|
hasReassociableOperands(*MI1, MBB) &&
|
|
MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
|
|
}
|
|
|
|
// 1. The operation must be associative and commutative.
|
|
// 2. The instruction must have virtual register definitions for its
|
|
// operands in the same basic block.
|
|
// 3. The instruction must have a reassociable sibling.
|
|
bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
|
|
bool &Commuted) const {
|
|
return isAssociativeAndCommutative(Inst) &&
|
|
hasReassociableOperands(Inst, Inst.getParent()) &&
|
|
hasReassociableSibling(Inst, Commuted);
|
|
}
|
|
|
|
// The concept of the reassociation pass is that these operations can benefit
|
|
// from this kind of transformation:
|
|
//
|
|
// A = ? op ?
|
|
// B = A op X (Prev)
|
|
// C = B op Y (Root)
|
|
// -->
|
|
// A = ? op ?
|
|
// B = X op Y
|
|
// C = A op B
|
|
//
|
|
// breaking the dependency between A and B, allowing them to be executed in
|
|
// parallel (or back-to-back in a pipeline) instead of depending on each other.
|
|
|
|
// FIXME: This has the potential to be expensive (compile time) while not
|
|
// improving the code at all. Some ways to limit the overhead:
|
|
// 1. Track successful transforms; bail out if hit rate gets too low.
|
|
// 2. Only enable at -O3 or some other non-default optimization level.
|
|
// 3. Pre-screen pattern candidates here: if an operand of the previous
|
|
// instruction is known to not increase the critical path, then don't match
|
|
// that pattern.
|
|
bool TargetInstrInfo::getMachineCombinerPatterns(
|
|
MachineInstr &Root,
|
|
SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
|
|
bool Commute;
|
|
if (isReassociationCandidate(Root, Commute)) {
|
|
// We found a sequence of instructions that may be suitable for a
|
|
// reassociation of operands to increase ILP. Specify each commutation
|
|
// possibility for the Prev instruction in the sequence and let the
|
|
// machine combiner decide if changing the operands is worthwhile.
|
|
if (Commute) {
|
|
Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
|
|
Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
|
|
} else {
|
|
Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
|
|
Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Return true when a code sequence can improve loop throughput.
|
|
bool
|
|
TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
|
|
return false;
|
|
}
|
|
|
|
/// Attempt the reassociation transformation to reduce critical path length.
|
|
/// See the above comments before getMachineCombinerPatterns().
|
|
void TargetInstrInfo::reassociateOps(
|
|
MachineInstr &Root, MachineInstr &Prev,
|
|
MachineCombinerPattern Pattern,
|
|
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
|
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
|
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
|
|
MachineFunction *MF = Root.getMF();
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
|
const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
|
|
|
|
// This array encodes the operand index for each parameter because the
|
|
// operands may be commuted. Each row corresponds to a pattern value,
|
|
// and each column specifies the index of A, B, X, Y.
|
|
unsigned OpIdx[4][4] = {
|
|
{ 1, 1, 2, 2 },
|
|
{ 1, 2, 2, 1 },
|
|
{ 2, 1, 1, 2 },
|
|
{ 2, 2, 1, 1 }
|
|
};
|
|
|
|
int Row;
|
|
switch (Pattern) {
|
|
case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
|
|
case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
|
|
case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
|
|
case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
|
|
default: llvm_unreachable("unexpected MachineCombinerPattern");
|
|
}
|
|
|
|
MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
|
|
MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
|
|
MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
|
|
MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
|
|
MachineOperand &OpC = Root.getOperand(0);
|
|
|
|
unsigned RegA = OpA.getReg();
|
|
unsigned RegB = OpB.getReg();
|
|
unsigned RegX = OpX.getReg();
|
|
unsigned RegY = OpY.getReg();
|
|
unsigned RegC = OpC.getReg();
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(RegA))
|
|
MRI.constrainRegClass(RegA, RC);
|
|
if (TargetRegisterInfo::isVirtualRegister(RegB))
|
|
MRI.constrainRegClass(RegB, RC);
|
|
if (TargetRegisterInfo::isVirtualRegister(RegX))
|
|
MRI.constrainRegClass(RegX, RC);
|
|
if (TargetRegisterInfo::isVirtualRegister(RegY))
|
|
MRI.constrainRegClass(RegY, RC);
|
|
if (TargetRegisterInfo::isVirtualRegister(RegC))
|
|
MRI.constrainRegClass(RegC, RC);
|
|
|
|
// Create a new virtual register for the result of (X op Y) instead of
|
|
// recycling RegB because the MachineCombiner's computation of the critical
|
|
// path requires a new register definition rather than an existing one.
|
|
unsigned NewVR = MRI.createVirtualRegister(RC);
|
|
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
|
|
|
|
unsigned Opcode = Root.getOpcode();
|
|
bool KillA = OpA.isKill();
|
|
bool KillX = OpX.isKill();
|
|
bool KillY = OpY.isKill();
|
|
|
|
// Create new instructions for insertion.
|
|
MachineInstrBuilder MIB1 =
|
|
BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
|
|
.addReg(RegX, getKillRegState(KillX))
|
|
.addReg(RegY, getKillRegState(KillY));
|
|
MachineInstrBuilder MIB2 =
|
|
BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
|
|
.addReg(RegA, getKillRegState(KillA))
|
|
.addReg(NewVR, getKillRegState(true));
|
|
|
|
setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
|
|
|
|
// Record new instructions for insertion and old instructions for deletion.
|
|
InsInstrs.push_back(MIB1);
|
|
InsInstrs.push_back(MIB2);
|
|
DelInstrs.push_back(&Prev);
|
|
DelInstrs.push_back(&Root);
|
|
}
|
|
|
|
void TargetInstrInfo::genAlternativeCodeSequence(
|
|
MachineInstr &Root, MachineCombinerPattern Pattern,
|
|
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
|
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
|
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
|
|
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
|
|
|
|
// Select the previous instruction in the sequence based on the input pattern.
|
|
MachineInstr *Prev = nullptr;
|
|
switch (Pattern) {
|
|
case MachineCombinerPattern::REASSOC_AX_BY:
|
|
case MachineCombinerPattern::REASSOC_XA_BY:
|
|
Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
|
|
break;
|
|
case MachineCombinerPattern::REASSOC_AX_YB:
|
|
case MachineCombinerPattern::REASSOC_XA_YB:
|
|
Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
assert(Prev && "Unknown pattern for machine combiner");
|
|
|
|
reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
|
|
}
|
|
|
|
void TargetInstrInfo::trackRegDefsUses(const MachineInstr &MI,
|
|
BitVector &ModifiedRegs,
|
|
BitVector &UsedRegs,
|
|
const TargetRegisterInfo *TRI) const {
|
|
for (const MachineOperand &MO : MI.operands()) {
|
|
if (MO.isRegMask())
|
|
ModifiedRegs.setBitsNotInMask(MO.getRegMask());
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!Reg)
|
|
continue;
|
|
if (MO.isDef()) {
|
|
// Some architectures (e.g. AArch64 XZR/WZR) have registers that are
|
|
// constant and may be used as destinations to indicate the generated
|
|
// value is discarded. No need to track such case as a def.
|
|
if (!TRI->isConstantPhysReg(Reg))
|
|
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
|
ModifiedRegs.set(*AI);
|
|
} else {
|
|
assert(MO.isUse() && "Reg operand not a def and not a use");
|
|
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
|
UsedRegs.set(*AI);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
|
|
const MachineInstr &MI, AliasAnalysis *AA) const {
|
|
const MachineFunction &MF = *MI.getMF();
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
// Remat clients assume operand 0 is the defined register.
|
|
if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
|
|
return false;
|
|
unsigned DefReg = MI.getOperand(0).getReg();
|
|
|
|
// A sub-register definition can only be rematerialized if the instruction
|
|
// doesn't read the other parts of the register. Otherwise it is really a
|
|
// read-modify-write operation on the full virtual register which cannot be
|
|
// moved safely.
|
|
if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
|
|
MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg))
|
|
return false;
|
|
|
|
// A load from a fixed stack slot can be rematerialized. This may be
|
|
// redundant with subsequent checks, but it's target-independent,
|
|
// simple, and a common case.
|
|
int FrameIdx = 0;
|
|
if (isLoadFromStackSlot(MI, FrameIdx) &&
|
|
MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
|
|
return true;
|
|
|
|
// Avoid instructions obviously unsafe for remat.
|
|
if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
|
|
return false;
|
|
|
|
// Don't remat inline asm. We have no idea how expensive it is
|
|
// even if it's side effect free.
|
|
if (MI.isInlineAsm())
|
|
return false;
|
|
|
|
// Avoid instructions which load from potentially varying memory.
|
|
if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
|
|
return false;
|
|
|
|
// If any of the registers accessed are non-constant, conservatively assume
|
|
// the instruction is not rematerializable.
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0)
|
|
continue;
|
|
|
|
// Check for a well-behaved physical register.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
if (MO.isUse()) {
|
|
// If the physreg has no defs anywhere, it's just an ambient register
|
|
// and we can freely move its uses. Alternatively, if it's allocatable,
|
|
// it could get allocated to something with a def during allocation.
|
|
if (!MRI.isConstantPhysReg(Reg))
|
|
return false;
|
|
} else {
|
|
// A physreg def. We can't remat it.
|
|
return false;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Only allow one virtual-register def. There may be multiple defs of the
|
|
// same virtual register, though.
|
|
if (MO.isDef() && Reg != DefReg)
|
|
return false;
|
|
|
|
// Don't allow any virtual-register uses. Rematting an instruction with
|
|
// virtual register uses would length the live ranges of the uses, which
|
|
// is not necessarily a good idea, certainly not "trivial".
|
|
if (MO.isUse())
|
|
return false;
|
|
}
|
|
|
|
// Everything checked out.
|
|
return true;
|
|
}
|
|
|
|
int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
|
|
const MachineFunction *MF = MI.getMF();
|
|
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
|
|
bool StackGrowsDown =
|
|
TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
|
|
|
|
unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
|
|
unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
|
|
|
|
if (!isFrameInstr(MI))
|
|
return 0;
|
|
|
|
int SPAdj = TFI->alignSPAdjust(getFrameSize(MI));
|
|
|
|
if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
|
|
(StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
|
|
SPAdj = -SPAdj;
|
|
|
|
return SPAdj;
|
|
}
|
|
|
|
/// isSchedulingBoundary - Test if the given instruction should be
|
|
/// considered a scheduling boundary. This primarily includes labels
|
|
/// and terminators.
|
|
bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const {
|
|
// Terminators and labels can't be scheduled around.
|
|
if (MI.isTerminator() || MI.isPosition())
|
|
return true;
|
|
|
|
// Don't attempt to schedule around any instruction that defines
|
|
// a stack-oriented pointer, as it's unlikely to be profitable. This
|
|
// saves compile time, because it doesn't require every single
|
|
// stack slot reference to depend on the instruction that does the
|
|
// modification.
|
|
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
|
|
}
|
|
|
|
// Provide a global flag for disabling the PreRA hazard recognizer that targets
|
|
// may choose to honor.
|
|
bool TargetInstrInfo::usePreRAHazardRecognizer() const {
|
|
return !DisableHazardRecognizer;
|
|
}
|
|
|
|
// Default implementation of CreateTargetRAHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
|
|
const ScheduleDAG *DAG) const {
|
|
// Dummy hazard recognizer allows all instructions to issue.
|
|
return new ScheduleHazardRecognizer();
|
|
}
|
|
|
|
// Default implementation of CreateTargetMIHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const {
|
|
return (ScheduleHazardRecognizer *)
|
|
new ScoreboardHazardRecognizer(II, DAG, "misched");
|
|
}
|
|
|
|
// Default implementation of CreateTargetPostRAHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const {
|
|
return (ScheduleHazardRecognizer *)
|
|
new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SelectionDAG latency interface.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
int
|
|
TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
|
SDNode *DefNode, unsigned DefIdx,
|
|
SDNode *UseNode, unsigned UseIdx) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return -1;
|
|
|
|
if (!DefNode->isMachineOpcode())
|
|
return -1;
|
|
|
|
unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
|
|
if (!UseNode->isMachineOpcode())
|
|
return ItinData->getOperandCycle(DefClass, DefIdx);
|
|
unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
|
|
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
|
}
|
|
|
|
int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
|
SDNode *N) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return 1;
|
|
|
|
if (!N->isMachineOpcode())
|
|
return 1;
|
|
|
|
return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MachineInstr latency interface.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
|
|
const MachineInstr &MI) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return 1;
|
|
|
|
unsigned Class = MI.getDesc().getSchedClass();
|
|
int UOps = ItinData->Itineraries[Class].NumMicroOps;
|
|
if (UOps >= 0)
|
|
return UOps;
|
|
|
|
// The # of u-ops is dynamically determined. The specific target should
|
|
// override this function to return the right number.
|
|
return 1;
|
|
}
|
|
|
|
/// Return the default expected latency for a def based on it's opcode.
|
|
unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
|
|
const MachineInstr &DefMI) const {
|
|
if (DefMI.isTransient())
|
|
return 0;
|
|
if (DefMI.mayLoad())
|
|
return SchedModel.LoadLatency;
|
|
if (isHighLatencyDef(DefMI.getOpcode()))
|
|
return SchedModel.HighLatency;
|
|
return 1;
|
|
}
|
|
|
|
unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
|
|
return 0;
|
|
}
|
|
|
|
unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr &MI,
|
|
unsigned *PredCost) const {
|
|
// Default to one cycle for no itinerary. However, an "empty" itinerary may
|
|
// still have a MinLatency property, which getStageLatency checks.
|
|
if (!ItinData)
|
|
return MI.mayLoad() ? 2 : 1;
|
|
|
|
return ItinData->getStageLatency(MI.getDesc().getSchedClass());
|
|
}
|
|
|
|
bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
|
|
const MachineInstr &DefMI,
|
|
unsigned DefIdx) const {
|
|
const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return false;
|
|
|
|
unsigned DefClass = DefMI.getDesc().getSchedClass();
|
|
int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
|
|
return (DefCycle != -1 && DefCycle <= 1);
|
|
}
|
|
|
|
/// Both DefMI and UseMI must be valid. By default, call directly to the
|
|
/// itinerary. This may be overriden by the target.
|
|
int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr &DefMI,
|
|
unsigned DefIdx,
|
|
const MachineInstr &UseMI,
|
|
unsigned UseIdx) const {
|
|
unsigned DefClass = DefMI.getDesc().getSchedClass();
|
|
unsigned UseClass = UseMI.getDesc().getSchedClass();
|
|
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
|
}
|
|
|
|
/// If we can determine the operand latency from the def only, without itinerary
|
|
/// lookup, do so. Otherwise return -1.
|
|
int TargetInstrInfo::computeDefOperandLatency(
|
|
const InstrItineraryData *ItinData, const MachineInstr &DefMI) const {
|
|
|
|
// Let the target hook getInstrLatency handle missing itineraries.
|
|
if (!ItinData)
|
|
return getInstrLatency(ItinData, DefMI);
|
|
|
|
if(ItinData->isEmpty())
|
|
return defaultDefLatency(ItinData->SchedModel, DefMI);
|
|
|
|
// ...operand lookup required
|
|
return -1;
|
|
}
|
|
|
|
bool TargetInstrInfo::getRegSequenceInputs(
|
|
const MachineInstr &MI, unsigned DefIdx,
|
|
SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
|
|
assert((MI.isRegSequence() ||
|
|
MI.isRegSequenceLike()) && "Instruction do not have the proper type");
|
|
|
|
if (!MI.isRegSequence())
|
|
return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
|
|
|
|
// We are looking at:
|
|
// Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
|
|
assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
|
|
for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
|
|
OpIdx += 2) {
|
|
const MachineOperand &MOReg = MI.getOperand(OpIdx);
|
|
if (MOReg.isUndef())
|
|
continue;
|
|
const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
|
|
assert(MOSubIdx.isImm() &&
|
|
"One of the subindex of the reg_sequence is not an immediate");
|
|
// Record Reg:SubReg, SubIdx.
|
|
InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
|
|
(unsigned)MOSubIdx.getImm()));
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool TargetInstrInfo::getExtractSubregInputs(
|
|
const MachineInstr &MI, unsigned DefIdx,
|
|
RegSubRegPairAndIdx &InputReg) const {
|
|
assert((MI.isExtractSubreg() ||
|
|
MI.isExtractSubregLike()) && "Instruction do not have the proper type");
|
|
|
|
if (!MI.isExtractSubreg())
|
|
return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
|
|
|
|
// We are looking at:
|
|
// Def = EXTRACT_SUBREG v0.sub1, sub0.
|
|
assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
|
|
const MachineOperand &MOReg = MI.getOperand(1);
|
|
if (MOReg.isUndef())
|
|
return false;
|
|
const MachineOperand &MOSubIdx = MI.getOperand(2);
|
|
assert(MOSubIdx.isImm() &&
|
|
"The subindex of the extract_subreg is not an immediate");
|
|
|
|
InputReg.Reg = MOReg.getReg();
|
|
InputReg.SubReg = MOReg.getSubReg();
|
|
InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
|
|
return true;
|
|
}
|
|
|
|
bool TargetInstrInfo::getInsertSubregInputs(
|
|
const MachineInstr &MI, unsigned DefIdx,
|
|
RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
|
|
assert((MI.isInsertSubreg() ||
|
|
MI.isInsertSubregLike()) && "Instruction do not have the proper type");
|
|
|
|
if (!MI.isInsertSubreg())
|
|
return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
|
|
|
|
// We are looking at:
|
|
// Def = INSERT_SEQUENCE v0, v1, sub0.
|
|
assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
|
|
const MachineOperand &MOBaseReg = MI.getOperand(1);
|
|
const MachineOperand &MOInsertedReg = MI.getOperand(2);
|
|
if (MOInsertedReg.isUndef())
|
|
return false;
|
|
const MachineOperand &MOSubIdx = MI.getOperand(3);
|
|
assert(MOSubIdx.isImm() &&
|
|
"One of the subindex of the reg_sequence is not an immediate");
|
|
BaseReg.Reg = MOBaseReg.getReg();
|
|
BaseReg.SubReg = MOBaseReg.getSubReg();
|
|
|
|
InsertedReg.Reg = MOInsertedReg.getReg();
|
|
InsertedReg.SubReg = MOInsertedReg.getSubReg();
|
|
InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
|
|
return true;
|
|
}
|