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5f3a6430d6
This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238723 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
5.6 KiB
C++
126 lines
5.6 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
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#define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class SITargetLowering : public AMDGPUTargetLowering {
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SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
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SDValue Chain, unsigned Offset, bool Signed) const;
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SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
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SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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SDValue performUCharToFloatCombine(SDNode *N,
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DAGCombinerInfo &DCI) const;
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SDValue performSHLPtrCombine(SDNode *N,
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unsigned AS,
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DAGCombinerInfo &DCI) const;
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SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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public:
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SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI);
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
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EVT /*VT*/) const override;
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bool isLegalAddressingMode(const AddrMode &AM,
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Type *Ty, unsigned AS) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
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unsigned Align,
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bool *IsFast) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset,
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bool ZeroMemset,
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bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(EVT VT) const override;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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MachineBasicBlock * BB) const override;
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bool enableAggressiveFMAFusion(EVT VT) const override;
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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MVT getScalarShiftAmountTy(EVT VT) const override;
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
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void AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const override;
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int32_t analyzeImmediate(const SDNode *N) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const override;
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void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
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MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const;
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MachineSDNode *buildRSRC(SelectionDAG &DAG,
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SDLoc DL,
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SDValue Ptr,
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uint32_t RsrcDword1,
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uint64_t RsrcDword2And3) const;
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MachineSDNode *buildScratchRSRC(SelectionDAG &DAG,
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SDLoc DL,
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SDValue Ptr) const;
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std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI,
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const std::string &Constraint, MVT VT) const override;
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SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;
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};
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} // End namespace llvm
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#endif
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