Matt Arsenault ac00e8c95b AMDGPU: Shrink insts to fold immediates ...

This needs to be done in the SSA fold operands
pass to be effective, so there is a bit of overlap
with SIShrinkInstructions but I don't think this
is practically avoidable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340859 91177308-0d34-0410-b5e6-96231b3b80d8

2018-08-28 18:34:24 +00:00

..

AArch64

[AArch64] Reject inline asm with FP registers when FP is disabled.

2018-08-24 19:12:13 +00:00

AMDGPU

AMDGPU: Shrink insts to fold immediates

2018-08-28 18:34:24 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.

2018-08-22 21:47:14 +00:00

AVR

[AVR] Set trackLivenessAfterRegAlloc

2018-06-11 14:46:48 +00:00

BPF

bpf: add missing RegState to notify MachineInstr verifier necessary register usage

2018-07-27 16:58:52 +00:00

Generic

[DWARF] Unclamp line table version on Darwin for v5 and later.

2018-08-08 21:16:50 +00:00

Hexagon

[Pipeliner] Fix incorrect phi values in the epilog and kernel

2018-08-27 22:04:50 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.

2018-08-28 03:47:20 +00:00

MIR

Consistently use MemoryLocation::UnknownSize to indicate unknown access size

2018-08-20 20:37:57 +00:00

MSP430

Emit a left-shift instead of a power-of-two multiply for jump-tables

2018-05-16 08:58:26 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[PPC] Remove Darwin support from POWER backend.

2018-08-28 01:18:29 +00:00

RISCV

[RISCV] atomic_store_nn have a different layout to regular store

2018-08-27 07:08:18 +00:00

SPARC

[Sparc] Add support for the cycle counter available in GR740

2018-08-27 11:11:47 +00:00

SystemZ

[PPC] Remove Darwin support from POWER backend.

2018-08-28 01:18:29 +00:00

Thumb

[SelectionDAG] Improve the legalisation lowering of UMULO.

2018-08-16 18:39:39 +00:00

Thumb2

[SelectionDAG] Improve the legalisation lowering of UMULO.

2018-08-16 18:39:39 +00:00

WebAssembly

[WebAssembly][NFC] Fix up SIMD bitwise tests

2018-08-28 18:33:31 +00:00

WinCFGuard

Rename the cfguard module flag to cfguardtable

2018-08-10 09:48:53 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Fix copy paste mistake in vector-idiv-v2i32.ll. Add missing test case.

2018-08-28 15:24:12 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00