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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
935 lines
32 KiB
C++
935 lines
32 KiB
C++
//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Pass to verify generated machine code. The following is checked:
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//
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// Operand counts: All explicit operands must be present.
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//
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// Register classes: All physical and virtual register operands must be
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// compatible with the register class required by the instruction descriptor.
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//
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// Register live intervals: Registers must be defined only once, and must be
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// defined before use.
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//
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// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
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// command-line option -verify-machineinstrs, or by defining the environment
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// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
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// the verifier errors.
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//===----------------------------------------------------------------------===//
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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struct MachineVerifier {
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MachineVerifier(Pass *pass) :
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PASS(pass),
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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
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{}
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bool runOnMachineFunction(MachineFunction &MF);
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Pass *const PASS;
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const char *const OutFileName;
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raw_ostream *OS;
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const MachineFunction *MF;
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const TargetMachine *TM;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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unsigned foundErrors;
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typedef SmallVector<unsigned, 16> RegVector;
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typedef DenseSet<unsigned> RegSet;
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typedef DenseMap<unsigned, const MachineInstr*> RegMap;
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BitVector regsReserved;
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RegSet regsLive;
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RegVector regsDefined, regsDead, regsKilled;
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RegSet regsLiveInButUnused;
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// Add Reg and any sub-registers to RV
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void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
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RV.push_back(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
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RV.push_back(*R);
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}
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struct BBInfo {
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// Is this MBB reachable from the MF entry point?
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bool reachable;
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// Vregs that must be live in because they are used without being
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// defined. Map value is the user.
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RegMap vregsLiveIn;
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// Regs killed in MBB. They may be defined again, and will then be in both
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// regsKilled and regsLiveOut.
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RegSet regsKilled;
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// Regs defined in MBB and live out. Note that vregs passing through may
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// be live out without being mentioned here.
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RegSet regsLiveOut;
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// Vregs that pass through MBB untouched. This set is disjoint from
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// regsKilled and regsLiveOut.
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RegSet vregsPassed;
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// Vregs that must pass through MBB because they are needed by a successor
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// block. This set is disjoint from regsLiveOut.
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RegSet vregsRequired;
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BBInfo() : reachable(false) {}
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// Add register to vregsPassed if it belongs there. Return true if
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// anything changed.
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bool addPassed(unsigned Reg) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return false;
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if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
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return false;
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return vregsPassed.insert(Reg).second;
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}
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// Same for a full set.
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bool addPassed(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addPassed(*I))
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changed = true;
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return changed;
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}
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// Add register to vregsRequired if it belongs there. Return true if
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// anything changed.
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bool addRequired(unsigned Reg) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return false;
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if (regsLiveOut.count(Reg))
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return false;
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return vregsRequired.insert(Reg).second;
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}
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// Same for a full set.
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bool addRequired(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addRequired(*I))
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changed = true;
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return changed;
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}
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// Same for a full map.
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bool addRequired(const RegMap &RM) {
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bool changed = false;
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for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
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if (addRequired(I->first))
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changed = true;
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return changed;
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}
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// Live-out registers are either in regsLiveOut or vregsPassed.
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bool isLiveOut(unsigned Reg) const {
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return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
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}
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};
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// Extra register info per MBB.
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DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
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bool isReserved(unsigned Reg) {
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return Reg < regsReserved.size() && regsReserved.test(Reg);
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}
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// Analysis information if available
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LiveVariables *LiveVars;
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const LiveIntervals *LiveInts;
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void visitMachineFunctionBefore();
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void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
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void visitMachineInstrBefore(const MachineInstr *MI);
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void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
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void visitMachineInstrAfter(const MachineInstr *MI);
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void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
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void visitMachineFunctionAfter();
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void report(const char *msg, const MachineFunction *MF);
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void report(const char *msg, const MachineBasicBlock *MBB);
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void report(const char *msg, const MachineInstr *MI);
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void report(const char *msg, const MachineOperand *MO, unsigned MONum);
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void markReachable(const MachineBasicBlock *MBB);
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void calcRegsPassed();
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void checkPHIOps(const MachineBasicBlock *MBB);
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void calcRegsRequired();
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void verifyLiveVariables();
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void verifyLiveIntervals();
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};
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struct MachineVerifierPass : public MachineFunctionPass {
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static char ID; // Pass ID, replacement for typeid
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MachineVerifierPass()
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: MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) {
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MF.verify(this);
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return false;
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}
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};
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}
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char MachineVerifierPass::ID = 0;
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static RegisterPass<MachineVerifierPass>
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MachineVer("machineverifier", "Verify generated machine code");
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static const PassInfo *const MachineVerifyID = &MachineVer;
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FunctionPass *llvm::createMachineVerifierPass() {
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return new MachineVerifierPass();
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}
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void MachineFunction::verify(Pass *p) const {
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MachineVerifier(p).runOnMachineFunction(const_cast<MachineFunction&>(*this));
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}
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bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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raw_ostream *OutFile = 0;
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if (OutFileName) {
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std::string ErrorInfo;
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OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
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raw_fd_ostream::F_Append);
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if (!ErrorInfo.empty()) {
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errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
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exit(1);
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}
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OS = OutFile;
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} else {
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OS = &errs();
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}
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foundErrors = 0;
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this->MF = &MF;
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TM = &MF.getTarget();
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TRI = TM->getRegisterInfo();
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MRI = &MF.getRegInfo();
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LiveVars = NULL;
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LiveInts = NULL;
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if (PASS) {
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LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
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// We don't want to verify LiveVariables if LiveIntervals is available.
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if (!LiveInts)
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LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
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}
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visitMachineFunctionBefore();
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for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
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MFI!=MFE; ++MFI) {
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visitMachineBasicBlockBefore(MFI);
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for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
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MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
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visitMachineInstrBefore(MBBI);
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for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
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visitMachineOperand(&MBBI->getOperand(I), I);
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visitMachineInstrAfter(MBBI);
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}
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visitMachineBasicBlockAfter(MFI);
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}
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visitMachineFunctionAfter();
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if (OutFile)
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delete OutFile;
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else if (foundErrors)
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report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
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// Clean up.
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regsLive.clear();
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regsDefined.clear();
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regsDead.clear();
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regsKilled.clear();
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regsLiveInButUnused.clear();
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MBBInfoMap.clear();
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return false; // no changes
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}
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void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
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assert(MF);
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*OS << '\n';
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if (!foundErrors++)
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MF->print(*OS);
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*OS << "*** Bad machine code: " << msg << " ***\n"
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<< "- function: " << MF->getFunction()->getNameStr() << "\n";
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
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assert(MBB);
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report(msg, MBB->getParent());
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*OS << "- basic block: " << MBB->getName()
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<< " " << (void*)MBB
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<< " (BB#" << MBB->getNumber() << ")\n";
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}
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void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
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assert(MI);
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report(msg, MI->getParent());
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*OS << "- instruction: ";
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MI->print(*OS, TM);
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}
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void MachineVerifier::report(const char *msg,
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const MachineOperand *MO, unsigned MONum) {
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assert(MO);
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report(msg, MO->getParent());
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*OS << "- operand " << MONum << ": ";
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MO->print(*OS, TM);
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*OS << "\n";
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}
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void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
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BBInfo &MInfo = MBBInfoMap[MBB];
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if (!MInfo.reachable) {
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MInfo.reachable = true;
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for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
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SuE = MBB->succ_end(); SuI != SuE; ++SuI)
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markReachable(*SuI);
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}
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}
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void MachineVerifier::visitMachineFunctionBefore() {
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regsReserved = TRI->getReservedRegs(*MF);
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// A sub-register of a reserved register is also reserved
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for (int Reg = regsReserved.find_first(); Reg>=0;
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Reg = regsReserved.find_next(Reg)) {
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for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
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// FIXME: This should probably be:
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// assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
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regsReserved.set(*Sub);
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}
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}
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markReachable(&MF->front());
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}
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// Does iterator point to a and b as the first two elements?
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static bool matchPair(MachineBasicBlock::const_succ_iterator i,
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const MachineBasicBlock *a, const MachineBasicBlock *b) {
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if (*i == a)
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return *++i == b;
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if (*i == b)
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return *++i == a;
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return false;
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}
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void
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MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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// Call AnalyzeBranch. If it succeeds, there several more conditions to check.
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MachineBasicBlock *TBB = 0, *FBB = 0;
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SmallVector<MachineOperand, 4> Cond;
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if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
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TBB, FBB, Cond)) {
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// Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
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// check whether its answers match up with reality.
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if (!TBB && !FBB) {
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// Block falls through to its successor.
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MachineFunction::const_iterator MBBI = MBB;
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++MBBI;
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if (MBBI == MF->end()) {
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// It's possible that the block legitimately ends with a noreturn
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// call or an unreachable, in which case it won't actually fall
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// out the bottom of the function.
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} else if (MBB->succ_empty()) {
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// It's possible that the block legitimately ends with a noreturn
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// call or an unreachable, in which case it won't actuall fall
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// out of the block.
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} else if (MBB->succ_size() != 1) {
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report("MBB exits via unconditional fall-through but doesn't have "
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"exactly one CFG successor!", MBB);
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} else if (MBB->succ_begin()[0] != MBBI) {
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report("MBB exits via unconditional fall-through but its successor "
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"differs from its CFG successor!", MBB);
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}
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if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
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!TII->isPredicated(&MBB->back())) {
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report("MBB exits via unconditional fall-through but ends with a "
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"barrier instruction!", MBB);
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}
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if (!Cond.empty()) {
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report("MBB exits via unconditional fall-through but has a condition!",
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MBB);
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}
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} else if (TBB && !FBB && Cond.empty()) {
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// Block unconditionally branches somewhere.
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if (MBB->succ_size() != 1) {
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report("MBB exits via unconditional branch but doesn't have "
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"exactly one CFG successor!", MBB);
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} else if (MBB->succ_begin()[0] != TBB) {
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report("MBB exits via unconditional branch but the CFG "
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"successor doesn't match the actual successor!", MBB);
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}
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if (MBB->empty()) {
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report("MBB exits via unconditional branch but doesn't contain "
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"any instructions!", MBB);
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} else if (!MBB->back().getDesc().isBarrier()) {
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report("MBB exits via unconditional branch but doesn't end with a "
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"barrier instruction!", MBB);
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} else if (!MBB->back().getDesc().isTerminator()) {
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report("MBB exits via unconditional branch but the branch isn't a "
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"terminator instruction!", MBB);
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}
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} else if (TBB && !FBB && !Cond.empty()) {
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// Block conditionally branches somewhere, otherwise falls through.
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MachineFunction::const_iterator MBBI = MBB;
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++MBBI;
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if (MBBI == MF->end()) {
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report("MBB conditionally falls through out of function!", MBB);
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} if (MBB->succ_size() != 2) {
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report("MBB exits via conditional branch/fall-through but doesn't have "
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"exactly two CFG successors!", MBB);
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} else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
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report("MBB exits via conditional branch/fall-through but the CFG "
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"successors don't match the actual successors!", MBB);
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}
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if (MBB->empty()) {
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report("MBB exits via conditional branch/fall-through but doesn't "
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"contain any instructions!", MBB);
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} else if (MBB->back().getDesc().isBarrier()) {
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report("MBB exits via conditional branch/fall-through but ends with a "
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"barrier instruction!", MBB);
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} else if (!MBB->back().getDesc().isTerminator()) {
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report("MBB exits via conditional branch/fall-through but the branch "
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"isn't a terminator instruction!", MBB);
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}
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} else if (TBB && FBB) {
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// Block conditionally branches somewhere, otherwise branches
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// somewhere else.
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if (MBB->succ_size() != 2) {
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report("MBB exits via conditional branch/branch but doesn't have "
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"exactly two CFG successors!", MBB);
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} else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
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report("MBB exits via conditional branch/branch but the CFG "
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"successors don't match the actual successors!", MBB);
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}
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if (MBB->empty()) {
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report("MBB exits via conditional branch/branch but doesn't "
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"contain any instructions!", MBB);
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} else if (!MBB->back().getDesc().isBarrier()) {
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report("MBB exits via conditional branch/branch but doesn't end with a "
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"barrier instruction!", MBB);
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} else if (!MBB->back().getDesc().isTerminator()) {
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report("MBB exits via conditional branch/branch but the branch "
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"isn't a terminator instruction!", MBB);
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}
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if (Cond.empty()) {
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report("MBB exits via conditinal branch/branch but there's no "
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"condition!", MBB);
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}
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} else {
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report("AnalyzeBranch returned invalid data!", MBB);
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}
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}
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regsLive.clear();
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for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I) {
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if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
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report("MBB live-in list contains non-physical register", MBB);
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continue;
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}
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regsLive.insert(*I);
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for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
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regsLive.insert(*R);
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}
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regsLiveInButUnused = regsLive;
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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assert(MFI && "Function has no frame info");
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BitVector PR = MFI->getPristineRegs(MBB);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
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regsLive.insert(I);
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for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
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regsLive.insert(*R);
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}
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|
|
regsKilled.clear();
|
|
regsDefined.clear();
|
|
}
|
|
|
|
void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
|
|
const TargetInstrDesc &TI = MI->getDesc();
|
|
if (MI->getNumOperands() < TI.getNumOperands()) {
|
|
report("Too few operands", MI);
|
|
*OS << TI.getNumOperands() << " operands expected, but "
|
|
<< MI->getNumExplicitOperands() << " given.\n";
|
|
}
|
|
|
|
// Check the MachineMemOperands for basic consistency.
|
|
for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
|
|
E = MI->memoperands_end(); I != E; ++I) {
|
|
if ((*I)->isLoad() && !TI.mayLoad())
|
|
report("Missing mayLoad flag", MI);
|
|
if ((*I)->isStore() && !TI.mayStore())
|
|
report("Missing mayStore flag", MI);
|
|
}
|
|
|
|
// Debug values must not have a slot index.
|
|
// Other instructions must have one.
|
|
if (LiveInts) {
|
|
bool mapped = !LiveInts->isNotInMIMap(MI);
|
|
if (MI->isDebugValue()) {
|
|
if (mapped)
|
|
report("Debug instruction has a slot index", MI);
|
|
} else {
|
|
if (!mapped)
|
|
report("Missing slot index", MI);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
|
|
const MachineInstr *MI = MO->getParent();
|
|
const TargetInstrDesc &TI = MI->getDesc();
|
|
|
|
// The first TI.NumDefs operands must be explicit register defines
|
|
if (MONum < TI.getNumDefs()) {
|
|
if (!MO->isReg())
|
|
report("Explicit definition must be a register", MO, MONum);
|
|
else if (!MO->isDef())
|
|
report("Explicit definition marked as use", MO, MONum);
|
|
else if (MO->isImplicit())
|
|
report("Explicit definition marked as implicit", MO, MONum);
|
|
} else if (MONum < TI.getNumOperands()) {
|
|
if (MO->isReg()) {
|
|
if (MO->isDef())
|
|
report("Explicit operand marked as def", MO, MONum);
|
|
if (MO->isImplicit())
|
|
report("Explicit operand marked as implicit", MO, MONum);
|
|
}
|
|
} else {
|
|
// ARM adds %reg0 operands to indicate predicates. We'll allow that.
|
|
if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
|
|
report("Extra explicit operand on non-variadic instruction", MO, MONum);
|
|
}
|
|
|
|
switch (MO->getType()) {
|
|
case MachineOperand::MO_Register: {
|
|
const unsigned Reg = MO->getReg();
|
|
if (!Reg)
|
|
return;
|
|
|
|
// Check Live Variables.
|
|
if (MO->isUndef()) {
|
|
// An <undef> doesn't refer to any register, so just skip it.
|
|
} else if (MO->isUse()) {
|
|
regsLiveInButUnused.erase(Reg);
|
|
|
|
bool isKill = false;
|
|
unsigned defIdx;
|
|
if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
|
|
// A two-addr use counts as a kill if use and def are the same.
|
|
unsigned DefReg = MI->getOperand(defIdx).getReg();
|
|
if (Reg == DefReg) {
|
|
isKill = true;
|
|
// ANd in that case an explicit kill flag is not allowed.
|
|
if (MO->isKill())
|
|
report("Illegal kill flag on two-address instruction operand",
|
|
MO, MONum);
|
|
} else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
report("Two-address instruction operands must be identical",
|
|
MO, MONum);
|
|
}
|
|
} else
|
|
isKill = MO->isKill();
|
|
|
|
if (isKill)
|
|
addRegWithSubRegs(regsKilled, Reg);
|
|
|
|
// Check that LiveVars knows this kill.
|
|
if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
MO->isKill()) {
|
|
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
|
|
if (std::find(VI.Kills.begin(),
|
|
VI.Kills.end(), MI) == VI.Kills.end())
|
|
report("Kill missing from LiveVariables", MO, MONum);
|
|
}
|
|
|
|
// Check LiveInts liveness and kill.
|
|
if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
|
|
SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
|
|
if (LiveInts->hasInterval(Reg)) {
|
|
const LiveInterval &LI = LiveInts->getInterval(Reg);
|
|
if (!LI.liveAt(UseIdx)) {
|
|
report("No live range at use", MO, MONum);
|
|
*OS << UseIdx << " is not live in " << LI << '\n';
|
|
}
|
|
// TODO: Verify isKill == LI.killedAt.
|
|
} else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
report("Virtual register has no Live interval", MO, MONum);
|
|
}
|
|
}
|
|
|
|
// Use of a dead register.
|
|
if (!regsLive.count(Reg)) {
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
// Reserved registers may be used even when 'dead'.
|
|
if (!isReserved(Reg))
|
|
report("Using an undefined physical register", MO, MONum);
|
|
} else {
|
|
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
|
|
// We don't know which virtual registers are live in, so only complain
|
|
// if vreg was killed in this MBB. Otherwise keep track of vregs that
|
|
// must be live in. PHI instructions are handled separately.
|
|
if (MInfo.regsKilled.count(Reg))
|
|
report("Using a killed virtual register", MO, MONum);
|
|
else if (!MI->isPHI())
|
|
MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
|
|
}
|
|
}
|
|
} else {
|
|
assert(MO->isDef());
|
|
// Register defined.
|
|
// TODO: verify that earlyclobber ops are not used.
|
|
if (MO->isDead())
|
|
addRegWithSubRegs(regsDead, Reg);
|
|
else
|
|
addRegWithSubRegs(regsDefined, Reg);
|
|
|
|
// Check LiveInts for a live range, but only for virtual registers.
|
|
if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
!LiveInts->isNotInMIMap(MI)) {
|
|
SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
|
|
if (LiveInts->hasInterval(Reg)) {
|
|
const LiveInterval &LI = LiveInts->getInterval(Reg);
|
|
if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) {
|
|
assert(LR->valno && "NULL valno is not allowed");
|
|
if (LR->valno->def != DefIdx) {
|
|
report("Inconsistent valno->def", MO, MONum);
|
|
*OS << "Valno " << LR->valno->id << " is not defined at "
|
|
<< DefIdx << " in " << LI << '\n';
|
|
}
|
|
} else {
|
|
report("No live range at def", MO, MONum);
|
|
*OS << DefIdx << " is not live in " << LI << '\n';
|
|
}
|
|
} else {
|
|
report("Virtual register has no Live interval", MO, MONum);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check register classes.
|
|
if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
|
|
const TargetOperandInfo &TOI = TI.OpInfo[MONum];
|
|
unsigned SubIdx = MO->getSubReg();
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
unsigned sr = Reg;
|
|
if (SubIdx) {
|
|
unsigned s = TRI->getSubReg(Reg, SubIdx);
|
|
if (!s) {
|
|
report("Invalid subregister index for physical register",
|
|
MO, MONum);
|
|
return;
|
|
}
|
|
sr = s;
|
|
}
|
|
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
|
|
if (!DRC->contains(sr)) {
|
|
report("Illegal physical register for instruction", MO, MONum);
|
|
*OS << TRI->getName(sr) << " is not a "
|
|
<< DRC->getName() << " register.\n";
|
|
}
|
|
}
|
|
} else {
|
|
// Virtual register.
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
if (SubIdx) {
|
|
const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
|
|
if (!SRC) {
|
|
report("Invalid subregister index for virtual register", MO, MONum);
|
|
*OS << "Register class " << RC->getName()
|
|
<< " does not support subreg index " << SubIdx << "\n";
|
|
return;
|
|
}
|
|
RC = SRC;
|
|
}
|
|
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
|
|
if (RC != DRC && !RC->hasSuperClass(DRC)) {
|
|
report("Illegal virtual register for instruction", MO, MONum);
|
|
*OS << "Expected a " << DRC->getName() << " register, but got a "
|
|
<< RC->getName() << " register\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
|
|
report("PHI operand is not in the CFG", MO, MONum);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
|
|
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
|
|
set_union(MInfo.regsKilled, regsKilled);
|
|
set_subtract(regsLive, regsKilled); regsKilled.clear();
|
|
set_subtract(regsLive, regsDead); regsDead.clear();
|
|
set_union(regsLive, regsDefined); regsDefined.clear();
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
|
|
MBBInfoMap[MBB].regsLiveOut = regsLive;
|
|
regsLive.clear();
|
|
}
|
|
|
|
// Calculate the largest possible vregsPassed sets. These are the registers that
|
|
// can pass through an MBB live, but may not be live every time. It is assumed
|
|
// that all vregsPassed sets are empty before the call.
|
|
void MachineVerifier::calcRegsPassed() {
|
|
// First push live-out regs to successors' vregsPassed. Remember the MBBs that
|
|
// have any vregsPassed.
|
|
DenseSet<const MachineBasicBlock*> todo;
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
const MachineBasicBlock &MBB(*MFI);
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
|
|
SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.regsLiveOut))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
|
|
// Iteratively push vregsPassed to successors. This will converge to the same
|
|
// final state regardless of DenseSet iteration order.
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
|
|
SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
|
|
if (*SuI == MBB)
|
|
continue;
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.vregsPassed))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate the set of virtual registers that must be passed through each basic
|
|
// block in order to satisfy the requirements of successor blocks. This is very
|
|
// similar to calcRegsPassed, only backwards.
|
|
void MachineVerifier::calcRegsRequired() {
|
|
// First push live-in regs to predecessors' vregsRequired.
|
|
DenseSet<const MachineBasicBlock*> todo;
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
const MachineBasicBlock &MBB(*MFI);
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
|
|
PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
|
|
BBInfo &PInfo = MBBInfoMap[*PrI];
|
|
if (PInfo.addRequired(MInfo.vregsLiveIn))
|
|
todo.insert(*PrI);
|
|
}
|
|
}
|
|
|
|
// Iteratively push vregsRequired to predecessors. This will converge to the
|
|
// same final state regardless of DenseSet iteration order.
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
if (*PrI == MBB)
|
|
continue;
|
|
BBInfo &SInfo = MBBInfoMap[*PrI];
|
|
if (SInfo.addRequired(MInfo.vregsRequired))
|
|
todo.insert(*PrI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check PHI instructions at the beginning of MBB. It is assumed that
|
|
// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
|
|
void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
|
|
for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
|
|
BBI != BBE && BBI->isPHI(); ++BBI) {
|
|
DenseSet<const MachineBasicBlock*> seen;
|
|
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
|
|
unsigned Reg = BBI->getOperand(i).getReg();
|
|
const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
|
|
if (!Pre->isSuccessor(MBB))
|
|
continue;
|
|
seen.insert(Pre);
|
|
BBInfo &PrInfo = MBBInfoMap[Pre];
|
|
if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
|
|
report("PHI operand is not live-out from predecessor",
|
|
&BBI->getOperand(i), i);
|
|
}
|
|
|
|
// Did we see all predecessors?
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
if (!seen.count(*PrI)) {
|
|
report("Missing PHI operand", BBI);
|
|
*OS << "BB#" << (*PrI)->getNumber()
|
|
<< " is a predecessor according to the CFG.\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineFunctionAfter() {
|
|
calcRegsPassed();
|
|
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
BBInfo &MInfo = MBBInfoMap[MFI];
|
|
|
|
// Skip unreachable MBBs.
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
|
|
checkPHIOps(MFI);
|
|
}
|
|
|
|
// Now check liveness info if available
|
|
if (LiveVars || LiveInts)
|
|
calcRegsRequired();
|
|
if (LiveVars)
|
|
verifyLiveVariables();
|
|
if (LiveInts)
|
|
verifyLiveIntervals();
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveVariables() {
|
|
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
|
|
for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
|
|
RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
|
|
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
BBInfo &MInfo = MBBInfoMap[MFI];
|
|
|
|
// Our vregsRequired should be identical to LiveVariables' AliveBlocks
|
|
if (MInfo.vregsRequired.count(Reg)) {
|
|
if (!VI.AliveBlocks.test(MFI->getNumber())) {
|
|
report("LiveVariables: Block missing from AliveBlocks", MFI);
|
|
*OS << "Virtual register %reg" << Reg
|
|
<< " must be live through the block.\n";
|
|
}
|
|
} else {
|
|
if (VI.AliveBlocks.test(MFI->getNumber())) {
|
|
report("LiveVariables: Block should not be in AliveBlocks", MFI);
|
|
*OS << "Virtual register %reg" << Reg
|
|
<< " is not needed live through the block.\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveIntervals() {
|
|
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
|
|
for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
|
|
LVE = LiveInts->end(); LVI != LVE; ++LVI) {
|
|
const LiveInterval &LI = *LVI->second;
|
|
assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
|
|
|
|
for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
|
|
I!=E; ++I) {
|
|
VNInfo *VNI = *I;
|
|
const LiveRange *DefLR = LI.getLiveRangeContaining(VNI->def);
|
|
|
|
if (!DefLR) {
|
|
if (!VNI->isUnused()) {
|
|
report("Valno not live at def and not marked unused", MF);
|
|
*OS << "Valno #" << VNI->id << " in " << LI << '\n';
|
|
}
|
|
continue;
|
|
}
|
|
|
|
if (VNI->isUnused())
|
|
continue;
|
|
|
|
if (DefLR->valno != VNI) {
|
|
report("Live range at def has different valno", MF);
|
|
DefLR->print(*OS);
|
|
*OS << " should use valno #" << VNI->id << " in " << LI << '\n';
|
|
}
|
|
|
|
}
|
|
|
|
for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
|
|
const LiveRange &LR = *I;
|
|
assert(LR.valno && "Live range has no valno");
|
|
|
|
if (LR.valno->id >= LI.getNumValNums() ||
|
|
LR.valno != LI.getValNumInfo(LR.valno->id)) {
|
|
report("Foreign valno in live range", MF);
|
|
LR.print(*OS);
|
|
*OS << " has a valno not in " << LI << '\n';
|
|
}
|
|
|
|
if (LR.valno->isUnused()) {
|
|
report("Live range valno is marked unused", MF);
|
|
LR.print(*OS);
|
|
*OS << " in " << LI << '\n';
|
|
}
|
|
|
|
}
|
|
}
|
|
}
|
|
|