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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
1423 lines
52 KiB
C++
1423 lines
52 KiB
C++
//===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine instruction level pre-register allocation
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// live interval splitting pass. It finds live interval barriers, i.e.
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// instructions which will kill all physical registers in certain register
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// classes, and split all live intervals which cross the barrier.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-alloc-split"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
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static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1),
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cl::Hidden);
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static cl::opt<int> RestoreFoldLimit("restore-fold-limit", cl::init(-1),
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cl::Hidden);
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STATISTIC(NumSplits, "Number of intervals split");
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STATISTIC(NumRemats, "Number of intervals split by rematerialization");
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STATISTIC(NumFolds, "Number of intervals split with spill folding");
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STATISTIC(NumRestoreFolds, "Number of intervals split with restore folding");
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STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
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STATISTIC(NumDeadSpills, "Number of dead spills removed");
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namespace {
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class PreAllocSplitting : public MachineFunctionPass {
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MachineFunction *CurrMF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo* TRI;
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MachineFrameInfo *MFI;
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MachineRegisterInfo *MRI;
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SlotIndexes *SIs;
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LiveIntervals *LIs;
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LiveStacks *LSs;
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VirtRegMap *VRM;
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// Barrier - Current barrier being processed.
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MachineInstr *Barrier;
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// BarrierMBB - Basic block where the barrier resides in.
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MachineBasicBlock *BarrierMBB;
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// Barrier - Current barrier index.
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SlotIndex BarrierIdx;
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// CurrLI - Current live interval being split.
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LiveInterval *CurrLI;
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// CurrSLI - Current stack slot live interval.
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LiveInterval *CurrSLI;
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// CurrSValNo - Current val# for the stack slot live interval.
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VNInfo *CurrSValNo;
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// IntervalSSMap - A map from live interval to spill slots.
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DenseMap<unsigned, int> IntervalSSMap;
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// Def2SpillMap - A map from a def instruction index to spill index.
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DenseMap<SlotIndex, SlotIndex> Def2SpillMap;
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public:
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static char ID;
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PreAllocSplitting()
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: MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addPreserved<RegisterCoalescer>();
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AU.addPreserved<CalculateSpillWeights>();
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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IntervalSSMap.clear();
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Def2SpillMap.clear();
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}
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virtual const char *getPassName() const {
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return "Pre-Register Allocaton Live Interval Splitting";
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}
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* M = 0) const {
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LIs->print(O, M);
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}
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private:
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MachineBasicBlock::iterator
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findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
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SmallPtrSet<MachineInstr*, 4>&);
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MachineBasicBlock::iterator
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findRestorePoint(MachineBasicBlock*, MachineInstr*, SlotIndex,
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SmallPtrSet<MachineInstr*, 4>&);
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int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
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bool IsAvailableInStack(MachineBasicBlock*, unsigned,
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SlotIndex, SlotIndex,
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SlotIndex&, int&) const;
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void UpdateSpillSlotInterval(VNInfo*, SlotIndex, SlotIndex);
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bool SplitRegLiveInterval(LiveInterval*);
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bool SplitRegLiveIntervals(const TargetRegisterClass **,
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SmallPtrSet<LiveInterval*, 8>&);
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bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
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MachineBasicBlock* BarrierMBB);
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bool Rematerialize(unsigned vreg, VNInfo* ValNo,
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MachineInstr* DefMI,
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MachineBasicBlock::iterator RestorePt,
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SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
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MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
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MachineInstr* DefMI,
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MachineInstr* Barrier,
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MachineBasicBlock* MBB,
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int& SS,
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SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
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MachineInstr* FoldRestore(unsigned vreg,
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const TargetRegisterClass* RC,
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MachineInstr* Barrier,
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MachineBasicBlock* MBB,
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int SS,
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SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
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void RenumberValno(VNInfo* VN);
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void ReconstructLiveInterval(LiveInterval* LI);
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bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
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unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
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unsigned Reg, int FrameIndex, bool& TwoAddr);
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VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use,
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MachineBasicBlock* MBB, LiveInterval* LI,
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SmallPtrSet<MachineInstr*, 4>& Visited,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
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DenseMap<MachineInstr*, VNInfo*>& NewVNs,
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DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
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DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
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bool IsTopLevel, bool IsIntraBlock);
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VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use,
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MachineBasicBlock* MBB, LiveInterval* LI,
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SmallPtrSet<MachineInstr*, 4>& Visited,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
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DenseMap<MachineInstr*, VNInfo*>& NewVNs,
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DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
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DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
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bool IsTopLevel, bool IsIntraBlock);
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};
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} // end anonymous namespace
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char PreAllocSplitting::ID = 0;
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static RegisterPass<PreAllocSplitting>
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X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
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char &llvm::PreAllocSplittingID = PreAllocSplitting::ID;
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/// findSpillPoint - Find a gap as far away from the given MI that's suitable
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/// for spilling the current live interval. The index must be before any
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/// defs and uses of the live interval register in the mbb. Return begin() if
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/// none is found.
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MachineBasicBlock::iterator
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PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
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MachineInstr *DefMI,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB) {
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MachineBasicBlock::iterator Pt = MBB->begin();
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MachineBasicBlock::iterator MII = MI;
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MachineBasicBlock::iterator EndPt = DefMI
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? MachineBasicBlock::iterator(DefMI) : MBB->begin();
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while (MII != EndPt && !RefsInMBB.count(MII) &&
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MII->getOpcode() != TRI->getCallFrameSetupOpcode())
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--MII;
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if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
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while (MII != EndPt && !RefsInMBB.count(MII)) {
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// We can't insert the spill between the barrier (a call), and its
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// corresponding call frame setup.
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if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
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while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
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--MII;
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if (MII == EndPt) {
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return Pt;
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}
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}
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continue;
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} else {
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Pt = MII;
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}
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if (RefsInMBB.count(MII))
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return Pt;
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--MII;
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}
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return Pt;
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}
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/// findRestorePoint - Find a gap in the instruction index map that's suitable
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/// for restoring the current live interval value. The index must be before any
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/// uses of the live interval register in the mbb. Return end() if none is
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/// found.
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MachineBasicBlock::iterator
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PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
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SlotIndex LastIdx,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB) {
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// FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
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// begin index accordingly.
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MachineBasicBlock::iterator Pt = MBB->end();
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MachineBasicBlock::iterator EndPt = MBB->getFirstTerminator();
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// We start at the call, so walk forward until we find the call frame teardown
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// since we can't insert restores before that. Bail if we encounter a use
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// during this time.
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MachineBasicBlock::iterator MII = MI;
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if (MII == EndPt) return Pt;
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while (MII != EndPt && !RefsInMBB.count(MII) &&
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MII->getOpcode() != TRI->getCallFrameDestroyOpcode())
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++MII;
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if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
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++MII;
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// FIXME: Limit the number of instructions to examine to reduce
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// compile time?
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while (MII != EndPt) {
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SlotIndex Index = LIs->getInstructionIndex(MII);
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if (Index > LastIdx)
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break;
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// We can't insert a restore between the barrier (a call) and its
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// corresponding call frame teardown.
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if (MII->getOpcode() == TRI->getCallFrameSetupOpcode()) {
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do {
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if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
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++MII;
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} while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
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} else {
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Pt = MII;
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}
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if (RefsInMBB.count(MII))
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return Pt;
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++MII;
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}
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return Pt;
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}
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/// CreateSpillStackSlot - Create a stack slot for the live interval being
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/// split. If the live interval was previously split, just reuse the same
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/// slot.
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int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
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const TargetRegisterClass *RC) {
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int SS;
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DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
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if (I != IntervalSSMap.end()) {
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SS = I->second;
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} else {
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SS = MFI->CreateSpillStackObject(RC->getSize(), RC->getAlignment());
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IntervalSSMap[Reg] = SS;
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}
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// Create live interval for stack slot.
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CurrSLI = &LSs->getOrCreateInterval(SS, RC);
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if (CurrSLI->hasAtLeastOneValue())
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CurrSValNo = CurrSLI->getValNumInfo(0);
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else
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CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, false,
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LSs->getVNInfoAllocator());
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return SS;
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}
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/// IsAvailableInStack - Return true if register is available in a split stack
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/// slot at the specified index.
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bool
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PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
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unsigned Reg, SlotIndex DefIndex,
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SlotIndex RestoreIndex,
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SlotIndex &SpillIndex,
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int& SS) const {
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if (!DefMBB)
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return false;
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DenseMap<unsigned, int>::const_iterator I = IntervalSSMap.find(Reg);
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if (I == IntervalSSMap.end())
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return false;
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DenseMap<SlotIndex, SlotIndex>::const_iterator
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II = Def2SpillMap.find(DefIndex);
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if (II == Def2SpillMap.end())
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return false;
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// If last spill of def is in the same mbb as barrier mbb (where restore will
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// be), make sure it's not below the intended restore index.
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// FIXME: Undo the previous spill?
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assert(LIs->getMBBFromIndex(II->second) == DefMBB);
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if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
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return false;
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SS = I->second;
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SpillIndex = II->second;
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return true;
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}
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/// UpdateSpillSlotInterval - Given the specified val# of the register live
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/// interval being split, and the spill and restore indicies, update the live
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/// interval of the spill stack slot.
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void
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PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, SlotIndex SpillIndex,
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SlotIndex RestoreIndex) {
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assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
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"Expect restore in the barrier mbb");
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MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
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if (MBB == BarrierMBB) {
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// Intra-block spill + restore. We are done.
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LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
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CurrSLI->addRange(SLR);
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return;
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}
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SmallPtrSet<MachineBasicBlock*, 4> Processed;
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SlotIndex EndIdx = LIs->getMBBEndIdx(MBB);
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LiveRange SLR(SpillIndex, EndIdx, CurrSValNo);
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CurrSLI->addRange(SLR);
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Processed.insert(MBB);
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// Start from the spill mbb, figure out the extend of the spill slot's
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// live interval.
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SmallVector<MachineBasicBlock*, 4> WorkList;
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const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
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if (LR->end > EndIdx)
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// If live range extend beyond end of mbb, add successors to work list.
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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while (!WorkList.empty()) {
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MachineBasicBlock *MBB = WorkList.back();
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WorkList.pop_back();
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if (Processed.count(MBB))
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continue;
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SlotIndex Idx = LIs->getMBBStartIdx(MBB);
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LR = CurrLI->getLiveRangeContaining(Idx);
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if (LR && LR->valno == ValNo) {
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EndIdx = LIs->getMBBEndIdx(MBB);
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if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
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// Spill slot live interval stops at the restore.
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LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
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CurrSLI->addRange(SLR);
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} else if (LR->end > EndIdx) {
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// Live range extends beyond end of mbb, process successors.
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LiveRange SLR(Idx, EndIdx.getNextIndex(), CurrSValNo);
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CurrSLI->addRange(SLR);
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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} else {
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LiveRange SLR(Idx, LR->end, CurrSValNo);
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CurrSLI->addRange(SLR);
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}
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Processed.insert(MBB);
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}
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}
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}
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/// PerformPHIConstruction - From properly set up use and def lists, use a PHI
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/// construction algorithm to compute the ranges and valnos for an interval.
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VNInfo*
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PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
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MachineBasicBlock* MBB, LiveInterval* LI,
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SmallPtrSet<MachineInstr*, 4>& Visited,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
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DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
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DenseMap<MachineInstr*, VNInfo*>& NewVNs,
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DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
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DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
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bool IsTopLevel, bool IsIntraBlock) {
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// Return memoized result if it's available.
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if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI))
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return NewVNs[UseI];
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else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI))
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return NewVNs[UseI];
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else if (!IsIntraBlock && LiveOut.count(MBB))
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return LiveOut[MBB];
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// Check if our block contains any uses or defs.
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bool ContainsDefs = Defs.count(MBB);
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bool ContainsUses = Uses.count(MBB);
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VNInfo* RetVNI = 0;
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// Enumerate the cases of use/def contaning blocks.
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if (!ContainsDefs && !ContainsUses) {
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return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
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NewVNs, LiveOut, Phis,
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IsTopLevel, IsIntraBlock);
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} else if (ContainsDefs && !ContainsUses) {
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SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
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// Search for the def in this block. If we don't find it before the
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// instruction we care about, go to the fallback case. Note that that
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// should never happen: this cannot be intrablock, so use should
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// always be an end() iterator.
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assert(UseI == MBB->end() && "No use marked in intrablock");
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MachineBasicBlock::iterator Walker = UseI;
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--Walker;
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|
while (Walker != MBB->begin()) {
|
|
if (BlockDefs.count(Walker))
|
|
break;
|
|
--Walker;
|
|
}
|
|
|
|
// Once we've found it, extend its VNInfo to our instruction.
|
|
SlotIndex DefIndex = LIs->getInstructionIndex(Walker);
|
|
DefIndex = DefIndex.getDefIndex();
|
|
SlotIndex EndIndex = LIs->getMBBEndIdx(MBB);
|
|
|
|
RetVNI = NewVNs[Walker];
|
|
LI->addRange(LiveRange(DefIndex, EndIndex, RetVNI));
|
|
} else if (!ContainsDefs && ContainsUses) {
|
|
SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
|
|
|
|
// Search for the use in this block that precedes the instruction we care
|
|
// about, going to the fallback case if we don't find it.
|
|
MachineBasicBlock::iterator Walker = UseI;
|
|
bool found = false;
|
|
while (Walker != MBB->begin()) {
|
|
--Walker;
|
|
if (BlockUses.count(Walker)) {
|
|
found = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!found)
|
|
return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
|
|
Uses, NewVNs, LiveOut, Phis,
|
|
IsTopLevel, IsIntraBlock);
|
|
|
|
SlotIndex UseIndex = LIs->getInstructionIndex(Walker);
|
|
UseIndex = UseIndex.getUseIndex();
|
|
SlotIndex EndIndex;
|
|
if (IsIntraBlock) {
|
|
EndIndex = LIs->getInstructionIndex(UseI).getDefIndex();
|
|
} else
|
|
EndIndex = LIs->getMBBEndIdx(MBB);
|
|
|
|
// Now, recursively phi construct the VNInfo for the use we found,
|
|
// and then extend it to include the instruction we care about
|
|
RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
|
|
NewVNs, LiveOut, Phis, false, true);
|
|
|
|
LI->addRange(LiveRange(UseIndex, EndIndex, RetVNI));
|
|
|
|
// FIXME: Need to set kills properly for inter-block stuff.
|
|
} else if (ContainsDefs && ContainsUses) {
|
|
SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
|
|
SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
|
|
|
|
// This case is basically a merging of the two preceding case, with the
|
|
// special note that checking for defs must take precedence over checking
|
|
// for uses, because of two-address instructions.
|
|
MachineBasicBlock::iterator Walker = UseI;
|
|
bool foundDef = false;
|
|
bool foundUse = false;
|
|
while (Walker != MBB->begin()) {
|
|
--Walker;
|
|
if (BlockDefs.count(Walker)) {
|
|
foundDef = true;
|
|
break;
|
|
} else if (BlockUses.count(Walker)) {
|
|
foundUse = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!foundDef && !foundUse)
|
|
return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
|
|
Uses, NewVNs, LiveOut, Phis,
|
|
IsTopLevel, IsIntraBlock);
|
|
|
|
SlotIndex StartIndex = LIs->getInstructionIndex(Walker);
|
|
StartIndex = foundDef ? StartIndex.getDefIndex() : StartIndex.getUseIndex();
|
|
SlotIndex EndIndex;
|
|
if (IsIntraBlock) {
|
|
EndIndex = LIs->getInstructionIndex(UseI).getDefIndex();
|
|
} else
|
|
EndIndex = LIs->getMBBEndIdx(MBB);
|
|
|
|
if (foundDef)
|
|
RetVNI = NewVNs[Walker];
|
|
else
|
|
RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
|
|
NewVNs, LiveOut, Phis, false, true);
|
|
|
|
LI->addRange(LiveRange(StartIndex, EndIndex, RetVNI));
|
|
}
|
|
|
|
// Memoize results so we don't have to recompute them.
|
|
if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
|
|
else {
|
|
if (!NewVNs.count(UseI))
|
|
NewVNs[UseI] = RetVNI;
|
|
Visited.insert(UseI);
|
|
}
|
|
|
|
return RetVNI;
|
|
}
|
|
|
|
/// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path.
|
|
///
|
|
VNInfo*
|
|
PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI,
|
|
MachineBasicBlock* MBB, LiveInterval* LI,
|
|
SmallPtrSet<MachineInstr*, 4>& Visited,
|
|
DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
|
|
DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
|
|
DenseMap<MachineInstr*, VNInfo*>& NewVNs,
|
|
DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
|
|
DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
|
|
bool IsTopLevel, bool IsIntraBlock) {
|
|
// NOTE: Because this is the fallback case from other cases, we do NOT
|
|
// assume that we are not intrablock here.
|
|
if (Phis.count(MBB)) return Phis[MBB];
|
|
|
|
SlotIndex StartIndex = LIs->getMBBStartIdx(MBB);
|
|
VNInfo *RetVNI = Phis[MBB] =
|
|
LI->getNextValue(SlotIndex(), /*FIXME*/ 0, false,
|
|
LIs->getVNInfoAllocator());
|
|
|
|
if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
|
|
|
|
// If there are no uses or defs between our starting point and the
|
|
// beginning of the block, then recursive perform phi construction
|
|
// on our predecessors.
|
|
DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
|
|
Visited, Defs, Uses, NewVNs,
|
|
LiveOut, Phis, false, false);
|
|
if (Incoming != 0)
|
|
IncomingVNs[*PI] = Incoming;
|
|
}
|
|
|
|
if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill()) {
|
|
VNInfo* OldVN = RetVNI;
|
|
VNInfo* NewVN = IncomingVNs.begin()->second;
|
|
VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN);
|
|
if (MergedVN == OldVN) std::swap(OldVN, NewVN);
|
|
|
|
for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator LOI = LiveOut.begin(),
|
|
LOE = LiveOut.end(); LOI != LOE; ++LOI)
|
|
if (LOI->second == OldVN)
|
|
LOI->second = MergedVN;
|
|
for (DenseMap<MachineInstr*, VNInfo*>::iterator NVI = NewVNs.begin(),
|
|
NVE = NewVNs.end(); NVI != NVE; ++NVI)
|
|
if (NVI->second == OldVN)
|
|
NVI->second = MergedVN;
|
|
for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator PI = Phis.begin(),
|
|
PE = Phis.end(); PI != PE; ++PI)
|
|
if (PI->second == OldVN)
|
|
PI->second = MergedVN;
|
|
RetVNI = MergedVN;
|
|
} else {
|
|
// Otherwise, merge the incoming VNInfos with a phi join. Create a new
|
|
// VNInfo to represent the joined value.
|
|
for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
|
|
IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
|
|
I->second->setHasPHIKill(true);
|
|
}
|
|
}
|
|
|
|
SlotIndex EndIndex;
|
|
if (IsIntraBlock) {
|
|
EndIndex = LIs->getInstructionIndex(UseI).getDefIndex();
|
|
} else
|
|
EndIndex = LIs->getMBBEndIdx(MBB);
|
|
LI->addRange(LiveRange(StartIndex, EndIndex, RetVNI));
|
|
|
|
// Memoize results so we don't have to recompute them.
|
|
if (!IsIntraBlock)
|
|
LiveOut[MBB] = RetVNI;
|
|
else {
|
|
if (!NewVNs.count(UseI))
|
|
NewVNs[UseI] = RetVNI;
|
|
Visited.insert(UseI);
|
|
}
|
|
|
|
return RetVNI;
|
|
}
|
|
|
|
/// ReconstructLiveInterval - Recompute a live interval from scratch.
|
|
void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
|
|
VNInfo::Allocator& Alloc = LIs->getVNInfoAllocator();
|
|
|
|
// Clear the old ranges and valnos;
|
|
LI->clear();
|
|
|
|
// Cache the uses and defs of the register
|
|
typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
|
|
RegMap Defs, Uses;
|
|
|
|
// Keep track of the new VNs we're creating.
|
|
DenseMap<MachineInstr*, VNInfo*> NewVNs;
|
|
SmallPtrSet<VNInfo*, 2> PhiVNs;
|
|
|
|
// Cache defs, and create a new VNInfo for each def.
|
|
for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
|
|
DE = MRI->def_end(); DI != DE; ++DI) {
|
|
Defs[(*DI).getParent()].insert(&*DI);
|
|
|
|
SlotIndex DefIdx = LIs->getInstructionIndex(&*DI);
|
|
DefIdx = DefIdx.getDefIndex();
|
|
|
|
assert(!DI->isPHI() && "PHI instr in code during pre-alloc splitting.");
|
|
VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
|
|
|
|
// If the def is a move, set the copy field.
|
|
if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
|
|
NewVN->setCopy(&*DI);
|
|
|
|
NewVNs[&*DI] = NewVN;
|
|
}
|
|
|
|
// Cache uses as a separate pass from actually processing them.
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
|
|
UE = MRI->use_end(); UI != UE; ++UI)
|
|
Uses[(*UI).getParent()].insert(&*UI);
|
|
|
|
// Now, actually process every use and use a phi construction algorithm
|
|
// to walk from it to its reaching definitions, building VNInfos along
|
|
// the way.
|
|
DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
|
|
DenseMap<MachineBasicBlock*, VNInfo*> Phis;
|
|
SmallPtrSet<MachineInstr*, 4> Visited;
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
|
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
|
PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
|
|
Uses, NewVNs, LiveOut, Phis, true, true);
|
|
}
|
|
|
|
// Add ranges for dead defs
|
|
for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
|
|
DE = MRI->def_end(); DI != DE; ++DI) {
|
|
SlotIndex DefIdx = LIs->getInstructionIndex(&*DI);
|
|
DefIdx = DefIdx.getDefIndex();
|
|
|
|
if (LI->liveAt(DefIdx)) continue;
|
|
|
|
VNInfo* DeadVN = NewVNs[&*DI];
|
|
LI->addRange(LiveRange(DefIdx, DefIdx.getNextSlot(), DeadVN));
|
|
}
|
|
}
|
|
|
|
/// RenumberValno - Split the given valno out into a new vreg, allowing it to
|
|
/// be allocated to a different register. This function creates a new vreg,
|
|
/// copies the valno and its live ranges over to the new vreg's interval,
|
|
/// removes them from the old interval, and rewrites all uses and defs of
|
|
/// the original reg to the new vreg within those ranges.
|
|
void PreAllocSplitting::RenumberValno(VNInfo* VN) {
|
|
SmallVector<VNInfo*, 4> Stack;
|
|
SmallVector<VNInfo*, 4> VNsToCopy;
|
|
Stack.push_back(VN);
|
|
|
|
// Walk through and copy the valno we care about, and any other valnos
|
|
// that are two-address redefinitions of the one we care about. These
|
|
// will need to be rewritten as well. We also check for safety of the
|
|
// renumbering here, by making sure that none of the valno involved has
|
|
// phi kills.
|
|
while (!Stack.empty()) {
|
|
VNInfo* OldVN = Stack.back();
|
|
Stack.pop_back();
|
|
|
|
// Bail out if we ever encounter a valno that has a PHI kill. We can't
|
|
// renumber these.
|
|
if (OldVN->hasPHIKill()) return;
|
|
|
|
VNsToCopy.push_back(OldVN);
|
|
|
|
// Locate two-address redefinitions
|
|
for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(CurrLI->reg),
|
|
DE = MRI->def_end(); DI != DE; ++DI) {
|
|
if (!DI->isRegTiedToUseOperand(DI.getOperandNo())) continue;
|
|
SlotIndex DefIdx = LIs->getInstructionIndex(&*DI).getDefIndex();
|
|
VNInfo* NextVN = CurrLI->findDefinedVNInfoForRegInt(DefIdx);
|
|
if (std::find(VNsToCopy.begin(), VNsToCopy.end(), NextVN) !=
|
|
VNsToCopy.end())
|
|
Stack.push_back(NextVN);
|
|
}
|
|
}
|
|
|
|
// Create the new vreg
|
|
unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
|
|
|
|
// Create the new live interval
|
|
LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
|
|
|
|
for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
|
|
VNsToCopy.end(); OI != OE; ++OI) {
|
|
VNInfo* OldVN = *OI;
|
|
|
|
// Copy the valno over
|
|
VNInfo* NewVN = NewLI.createValueCopy(OldVN, LIs->getVNInfoAllocator());
|
|
NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
|
|
|
|
// Remove the valno from the old interval
|
|
CurrLI->removeValNo(OldVN);
|
|
}
|
|
|
|
// Rewrite defs and uses. This is done in two stages to avoid invalidating
|
|
// the reg_iterator.
|
|
SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
|
|
|
|
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
|
|
E = MRI->reg_end(); I != E; ++I) {
|
|
MachineOperand& MO = I.getOperand();
|
|
SlotIndex InstrIdx = LIs->getInstructionIndex(&*I);
|
|
|
|
if ((MO.isUse() && NewLI.liveAt(InstrIdx.getUseIndex())) ||
|
|
(MO.isDef() && NewLI.liveAt(InstrIdx.getDefIndex())))
|
|
OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
|
|
}
|
|
|
|
for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
|
|
OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
|
|
MachineInstr* Inst = I->first;
|
|
unsigned OpIdx = I->second;
|
|
MachineOperand& MO = Inst->getOperand(OpIdx);
|
|
MO.setReg(NewVReg);
|
|
}
|
|
|
|
// Grow the VirtRegMap, since we've created a new vreg.
|
|
VRM->grow();
|
|
|
|
// The renumbered vreg shares a stack slot with the old register.
|
|
if (IntervalSSMap.count(CurrLI->reg))
|
|
IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
|
|
|
|
++NumRenumbers;
|
|
}
|
|
|
|
bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
|
|
MachineInstr* DefMI,
|
|
MachineBasicBlock::iterator RestorePt,
|
|
SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
|
|
MachineBasicBlock& MBB = *RestorePt->getParent();
|
|
|
|
MachineBasicBlock::iterator KillPt = BarrierMBB->end();
|
|
if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
|
|
KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB);
|
|
else
|
|
KillPt = llvm::next(MachineBasicBlock::iterator(DefMI));
|
|
|
|
if (KillPt == DefMI->getParent()->end())
|
|
return false;
|
|
|
|
TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, *TRI);
|
|
SlotIndex RematIdx = LIs->InsertMachineInstrInMaps(prior(RestorePt));
|
|
|
|
ReconstructLiveInterval(CurrLI);
|
|
RematIdx = RematIdx.getDefIndex();
|
|
RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx));
|
|
|
|
++NumSplits;
|
|
++NumRemats;
|
|
return true;
|
|
}
|
|
|
|
MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
|
|
const TargetRegisterClass* RC,
|
|
MachineInstr* DefMI,
|
|
MachineInstr* Barrier,
|
|
MachineBasicBlock* MBB,
|
|
int& SS,
|
|
SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
|
|
// Go top down if RefsInMBB is empty.
|
|
if (RefsInMBB.empty())
|
|
return 0;
|
|
|
|
MachineBasicBlock::iterator FoldPt = Barrier;
|
|
while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
|
|
!RefsInMBB.count(FoldPt))
|
|
--FoldPt;
|
|
|
|
int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg);
|
|
if (OpIdx == -1)
|
|
return 0;
|
|
|
|
SmallVector<unsigned, 1> Ops;
|
|
Ops.push_back(OpIdx);
|
|
|
|
if (!TII->canFoldMemoryOperand(FoldPt, Ops))
|
|
return 0;
|
|
|
|
DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
|
|
if (I != IntervalSSMap.end()) {
|
|
SS = I->second;
|
|
} else {
|
|
SS = MFI->CreateSpillStackObject(RC->getSize(), RC->getAlignment());
|
|
}
|
|
|
|
MachineInstr* FMI = TII->foldMemoryOperand(FoldPt, Ops, SS);
|
|
|
|
if (FMI) {
|
|
LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
|
|
FoldPt->eraseFromParent();
|
|
++NumFolds;
|
|
|
|
IntervalSSMap[vreg] = SS;
|
|
CurrSLI = &LSs->getOrCreateInterval(SS, RC);
|
|
if (CurrSLI->hasAtLeastOneValue())
|
|
CurrSValNo = CurrSLI->getValNumInfo(0);
|
|
else
|
|
CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, false,
|
|
LSs->getVNInfoAllocator());
|
|
}
|
|
|
|
return FMI;
|
|
}
|
|
|
|
MachineInstr* PreAllocSplitting::FoldRestore(unsigned vreg,
|
|
const TargetRegisterClass* RC,
|
|
MachineInstr* Barrier,
|
|
MachineBasicBlock* MBB,
|
|
int SS,
|
|
SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
|
|
if ((int)RestoreFoldLimit != -1 && RestoreFoldLimit == (int)NumRestoreFolds)
|
|
return 0;
|
|
|
|
// Go top down if RefsInMBB is empty.
|
|
if (RefsInMBB.empty())
|
|
return 0;
|
|
|
|
// Can't fold a restore between a call stack setup and teardown.
|
|
MachineBasicBlock::iterator FoldPt = Barrier;
|
|
|
|
// Advance from barrier to call frame teardown.
|
|
while (FoldPt != MBB->getFirstTerminator() &&
|
|
FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
|
|
if (RefsInMBB.count(FoldPt))
|
|
return 0;
|
|
|
|
++FoldPt;
|
|
}
|
|
|
|
if (FoldPt == MBB->getFirstTerminator())
|
|
return 0;
|
|
else
|
|
++FoldPt;
|
|
|
|
// Now find the restore point.
|
|
while (FoldPt != MBB->getFirstTerminator() && !RefsInMBB.count(FoldPt)) {
|
|
if (FoldPt->getOpcode() == TRI->getCallFrameSetupOpcode()) {
|
|
while (FoldPt != MBB->getFirstTerminator() &&
|
|
FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
|
|
if (RefsInMBB.count(FoldPt))
|
|
return 0;
|
|
|
|
++FoldPt;
|
|
}
|
|
|
|
if (FoldPt == MBB->getFirstTerminator())
|
|
return 0;
|
|
}
|
|
|
|
++FoldPt;
|
|
}
|
|
|
|
if (FoldPt == MBB->getFirstTerminator())
|
|
return 0;
|
|
|
|
int OpIdx = FoldPt->findRegisterUseOperandIdx(vreg, true);
|
|
if (OpIdx == -1)
|
|
return 0;
|
|
|
|
SmallVector<unsigned, 1> Ops;
|
|
Ops.push_back(OpIdx);
|
|
|
|
if (!TII->canFoldMemoryOperand(FoldPt, Ops))
|
|
return 0;
|
|
|
|
MachineInstr* FMI = TII->foldMemoryOperand(FoldPt, Ops, SS);
|
|
|
|
if (FMI) {
|
|
LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
|
|
FoldPt->eraseFromParent();
|
|
++NumRestoreFolds;
|
|
}
|
|
|
|
return FMI;
|
|
}
|
|
|
|
/// SplitRegLiveInterval - Split (spill and restore) the given live interval
|
|
/// so it would not cross the barrier that's being processed. Shrink wrap
|
|
/// (minimize) the live interval to the last uses.
|
|
bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
|
|
DEBUG(dbgs() << "Pre-alloc splitting " << LI->reg << " for " << *Barrier
|
|
<< " result: ");
|
|
|
|
CurrLI = LI;
|
|
|
|
// Find live range where current interval cross the barrier.
|
|
LiveInterval::iterator LR =
|
|
CurrLI->FindLiveRangeContaining(BarrierIdx.getUseIndex());
|
|
VNInfo *ValNo = LR->valno;
|
|
|
|
assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
|
|
|
|
MachineInstr *DefMI = ValNo->isDefAccurate()
|
|
? LIs->getInstructionFromIndex(ValNo->def) : NULL;
|
|
|
|
// If this would create a new join point, do not split.
|
|
if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent())) {
|
|
DEBUG(dbgs() << "FAILED (would create a new join point).\n");
|
|
return false;
|
|
}
|
|
|
|
// Find all references in the barrier mbb.
|
|
SmallPtrSet<MachineInstr*, 4> RefsInMBB;
|
|
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
|
|
E = MRI->reg_end(); I != E; ++I) {
|
|
MachineInstr *RefMI = &*I;
|
|
if (RefMI->getParent() == BarrierMBB)
|
|
RefsInMBB.insert(RefMI);
|
|
}
|
|
|
|
// Find a point to restore the value after the barrier.
|
|
MachineBasicBlock::iterator RestorePt =
|
|
findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB);
|
|
if (RestorePt == BarrierMBB->end()) {
|
|
DEBUG(dbgs() << "FAILED (could not find a suitable restore point).\n");
|
|
return false;
|
|
}
|
|
|
|
if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
|
|
if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt, RefsInMBB)) {
|
|
DEBUG(dbgs() << "success (remat).\n");
|
|
return true;
|
|
}
|
|
|
|
// Add a spill either before the barrier or after the definition.
|
|
MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
|
|
const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
|
|
SlotIndex SpillIndex;
|
|
MachineInstr *SpillMI = NULL;
|
|
int SS = -1;
|
|
if (!ValNo->isDefAccurate()) {
|
|
// If we don't know where the def is we must split just before the barrier.
|
|
if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
|
|
BarrierMBB, SS, RefsInMBB))) {
|
|
SpillIndex = LIs->getInstructionIndex(SpillMI);
|
|
} else {
|
|
MachineBasicBlock::iterator SpillPt =
|
|
findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB);
|
|
if (SpillPt == BarrierMBB->begin()) {
|
|
DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n");
|
|
return false; // No gap to insert spill.
|
|
}
|
|
// Add spill.
|
|
|
|
SS = CreateSpillStackSlot(CurrLI->reg, RC);
|
|
TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC,
|
|
TRI);
|
|
SpillMI = prior(SpillPt);
|
|
SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI);
|
|
}
|
|
} else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
|
|
LIs->getZeroIndex(), SpillIndex, SS)) {
|
|
// If it's already split, just restore the value. There is no need to spill
|
|
// the def again.
|
|
if (!DefMI) {
|
|
DEBUG(dbgs() << "FAILED (def is dead).\n");
|
|
return false; // Def is dead. Do nothing.
|
|
}
|
|
|
|
if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
|
|
BarrierMBB, SS, RefsInMBB))) {
|
|
SpillIndex = LIs->getInstructionIndex(SpillMI);
|
|
} else {
|
|
// Check if it's possible to insert a spill after the def MI.
|
|
MachineBasicBlock::iterator SpillPt;
|
|
if (DefMBB == BarrierMBB) {
|
|
// Add spill after the def and the last use before the barrier.
|
|
SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
|
|
RefsInMBB);
|
|
if (SpillPt == DefMBB->begin()) {
|
|
DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n");
|
|
return false; // No gap to insert spill.
|
|
}
|
|
} else {
|
|
SpillPt = llvm::next(MachineBasicBlock::iterator(DefMI));
|
|
if (SpillPt == DefMBB->end()) {
|
|
DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n");
|
|
return false; // No gap to insert spill.
|
|
}
|
|
}
|
|
// Add spill.
|
|
SS = CreateSpillStackSlot(CurrLI->reg, RC);
|
|
TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC,
|
|
TRI);
|
|
SpillMI = prior(SpillPt);
|
|
SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI);
|
|
}
|
|
}
|
|
|
|
// Remember def instruction index to spill index mapping.
|
|
if (DefMI && SpillMI)
|
|
Def2SpillMap[ValNo->def] = SpillIndex;
|
|
|
|
// Add restore.
|
|
bool FoldedRestore = false;
|
|
SlotIndex RestoreIndex;
|
|
if (MachineInstr* LMI = FoldRestore(CurrLI->reg, RC, Barrier,
|
|
BarrierMBB, SS, RefsInMBB)) {
|
|
RestorePt = LMI;
|
|
RestoreIndex = LIs->getInstructionIndex(RestorePt);
|
|
FoldedRestore = true;
|
|
} else {
|
|
TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC, TRI);
|
|
MachineInstr *LoadMI = prior(RestorePt);
|
|
RestoreIndex = LIs->InsertMachineInstrInMaps(LoadMI);
|
|
}
|
|
|
|
// Update spill stack slot live interval.
|
|
UpdateSpillSlotInterval(ValNo, SpillIndex.getUseIndex().getNextSlot(),
|
|
RestoreIndex.getDefIndex());
|
|
|
|
ReconstructLiveInterval(CurrLI);
|
|
|
|
if (!FoldedRestore) {
|
|
SlotIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
|
|
RestoreIdx = RestoreIdx.getDefIndex();
|
|
RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx));
|
|
}
|
|
|
|
++NumSplits;
|
|
DEBUG(dbgs() << "success.\n");
|
|
return true;
|
|
}
|
|
|
|
/// SplitRegLiveIntervals - Split all register live intervals that cross the
|
|
/// barrier that's being processed.
|
|
bool
|
|
PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
|
|
SmallPtrSet<LiveInterval*, 8>& Split) {
|
|
// First find all the virtual registers whose live intervals are intercepted
|
|
// by the current barrier.
|
|
SmallVector<LiveInterval*, 8> Intervals;
|
|
for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
|
|
// FIXME: If it's not safe to move any instruction that defines the barrier
|
|
// register class, then it means there are some special dependencies which
|
|
// codegen is not modelling. Ignore these barriers for now.
|
|
if (!TII->isSafeToMoveRegClassDefs(*RC))
|
|
continue;
|
|
const std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
|
|
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
|
|
unsigned Reg = VRs[i];
|
|
if (!LIs->hasInterval(Reg))
|
|
continue;
|
|
LiveInterval *LI = &LIs->getInterval(Reg);
|
|
if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
|
|
// Virtual register live interval is intercepted by the barrier. We
|
|
// should split and shrink wrap its interval if possible.
|
|
Intervals.push_back(LI);
|
|
}
|
|
}
|
|
|
|
// Process the affected live intervals.
|
|
bool Change = false;
|
|
while (!Intervals.empty()) {
|
|
if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
|
|
break;
|
|
LiveInterval *LI = Intervals.back();
|
|
Intervals.pop_back();
|
|
bool result = SplitRegLiveInterval(LI);
|
|
if (result) Split.insert(LI);
|
|
Change |= result;
|
|
}
|
|
|
|
return Change;
|
|
}
|
|
|
|
unsigned PreAllocSplitting::getNumberOfNonSpills(
|
|
SmallPtrSet<MachineInstr*, 4>& MIs,
|
|
unsigned Reg, int FrameIndex,
|
|
bool& FeedsTwoAddr) {
|
|
unsigned NonSpills = 0;
|
|
for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
|
|
UI != UE; ++UI) {
|
|
int StoreFrameIndex;
|
|
unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
|
|
if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
|
|
++NonSpills;
|
|
|
|
int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
|
|
if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx))
|
|
FeedsTwoAddr = true;
|
|
}
|
|
|
|
return NonSpills;
|
|
}
|
|
|
|
/// removeDeadSpills - After doing splitting, filter through all intervals we've
|
|
/// split, and see if any of the spills are unnecessary. If so, remove them.
|
|
bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
|
|
bool changed = false;
|
|
|
|
// Walk over all of the live intervals that were touched by the splitter,
|
|
// and see if we can do any DCE and/or folding.
|
|
for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
|
|
LE = split.end(); LI != LE; ++LI) {
|
|
DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
|
|
|
|
// First, collect all the uses of the vreg, and sort them by their
|
|
// reaching definition (VNInfo).
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
|
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
|
SlotIndex index = LIs->getInstructionIndex(&*UI);
|
|
index = index.getUseIndex();
|
|
|
|
const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
|
|
VNUseCount[LR->valno].insert(&*UI);
|
|
}
|
|
|
|
// Now, take the definitions (VNInfo's) one at a time and try to DCE
|
|
// and/or fold them away.
|
|
for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
|
|
VE = (*LI)->vni_end(); VI != VE; ++VI) {
|
|
|
|
if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
|
|
return changed;
|
|
|
|
VNInfo* CurrVN = *VI;
|
|
|
|
// We don't currently try to handle definitions with PHI kills, because
|
|
// it would involve processing more than one VNInfo at once.
|
|
if (CurrVN->hasPHIKill()) continue;
|
|
|
|
// We also don't try to handle the results of PHI joins, since there's
|
|
// no defining instruction to analyze.
|
|
if (!CurrVN->isDefAccurate() || CurrVN->isUnused()) continue;
|
|
|
|
// We're only interested in eliminating cruft introduced by the splitter,
|
|
// is of the form load-use or load-use-store. First, check that the
|
|
// definition is a load, and remember what stack slot we loaded it from.
|
|
MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def);
|
|
int FrameIndex;
|
|
if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
|
|
|
|
// If the definition has no uses at all, just DCE it.
|
|
if (VNUseCount[CurrVN].size() == 0) {
|
|
LIs->RemoveMachineInstrFromMaps(DefMI);
|
|
(*LI)->removeValNo(CurrVN);
|
|
DefMI->eraseFromParent();
|
|
VNUseCount.erase(CurrVN);
|
|
++NumDeadSpills;
|
|
changed = true;
|
|
continue;
|
|
}
|
|
|
|
// Second, get the number of non-store uses of the definition, as well as
|
|
// a flag indicating whether it feeds into a later two-address definition.
|
|
bool FeedsTwoAddr = false;
|
|
unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
|
|
(*LI)->reg, FrameIndex,
|
|
FeedsTwoAddr);
|
|
|
|
// If there's one non-store use and it doesn't feed a two-addr, then
|
|
// this is a load-use-store case that we can try to fold.
|
|
if (NonSpillCount == 1 && !FeedsTwoAddr) {
|
|
// Start by finding the non-store use MachineInstr.
|
|
SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
|
|
int StoreFrameIndex;
|
|
unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
|
|
while (UI != VNUseCount[CurrVN].end() &&
|
|
(StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
|
|
++UI;
|
|
if (UI != VNUseCount[CurrVN].end())
|
|
StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
|
|
}
|
|
if (UI == VNUseCount[CurrVN].end()) continue;
|
|
|
|
MachineInstr* use = *UI;
|
|
|
|
// Attempt to fold it away!
|
|
int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
|
|
if (OpIdx == -1) continue;
|
|
SmallVector<unsigned, 1> Ops;
|
|
Ops.push_back(OpIdx);
|
|
if (!TII->canFoldMemoryOperand(use, Ops)) continue;
|
|
|
|
MachineInstr* NewMI = TII->foldMemoryOperand(use, Ops, FrameIndex);
|
|
|
|
if (!NewMI) continue;
|
|
|
|
// Update relevant analyses.
|
|
LIs->RemoveMachineInstrFromMaps(DefMI);
|
|
LIs->ReplaceMachineInstrInMaps(use, NewMI);
|
|
(*LI)->removeValNo(CurrVN);
|
|
|
|
DefMI->eraseFromParent();
|
|
use->eraseFromParent();
|
|
VNUseCount[CurrVN].erase(use);
|
|
|
|
// Remove deleted instructions. Note that we need to remove them from
|
|
// the VNInfo->use map as well, just to be safe.
|
|
for (SmallPtrSet<MachineInstr*, 4>::iterator II =
|
|
VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
|
|
II != IE; ++II) {
|
|
for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
|
|
VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
|
|
++VNI)
|
|
if (VNI->first != CurrVN)
|
|
VNI->second.erase(*II);
|
|
LIs->RemoveMachineInstrFromMaps(*II);
|
|
(*II)->eraseFromParent();
|
|
}
|
|
|
|
VNUseCount.erase(CurrVN);
|
|
|
|
for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
|
|
VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
|
|
if (VI->second.erase(use))
|
|
VI->second.insert(NewMI);
|
|
|
|
++NumDeadSpills;
|
|
changed = true;
|
|
continue;
|
|
}
|
|
|
|
// If there's more than one non-store instruction, we can't profitably
|
|
// fold it, so bail.
|
|
if (NonSpillCount) continue;
|
|
|
|
// Otherwise, this is a load-store case, so DCE them.
|
|
for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
|
|
VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
|
|
UI != UE; ++UI) {
|
|
LIs->RemoveMachineInstrFromMaps(*UI);
|
|
(*UI)->eraseFromParent();
|
|
}
|
|
|
|
VNUseCount.erase(CurrVN);
|
|
|
|
LIs->RemoveMachineInstrFromMaps(DefMI);
|
|
(*LI)->removeValNo(CurrVN);
|
|
DefMI->eraseFromParent();
|
|
++NumDeadSpills;
|
|
changed = true;
|
|
}
|
|
}
|
|
|
|
return changed;
|
|
}
|
|
|
|
bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
|
|
MachineBasicBlock* DefMBB,
|
|
MachineBasicBlock* BarrierMBB) {
|
|
if (DefMBB == BarrierMBB)
|
|
return false;
|
|
|
|
if (LR->valno->hasPHIKill())
|
|
return false;
|
|
|
|
SlotIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
|
|
if (LR->end < MBBEnd)
|
|
return false;
|
|
|
|
MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
|
|
if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
|
|
return true;
|
|
|
|
MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
|
|
SmallPtrSet<MachineBasicBlock*, 4> Visited;
|
|
typedef std::pair<MachineBasicBlock*,
|
|
MachineBasicBlock::succ_iterator> ItPair;
|
|
SmallVector<ItPair, 4> Stack;
|
|
Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
|
|
|
|
while (!Stack.empty()) {
|
|
ItPair P = Stack.back();
|
|
Stack.pop_back();
|
|
|
|
MachineBasicBlock* PredMBB = P.first;
|
|
MachineBasicBlock::succ_iterator S = P.second;
|
|
|
|
if (S == PredMBB->succ_end())
|
|
continue;
|
|
else if (Visited.count(*S)) {
|
|
Stack.push_back(std::make_pair(PredMBB, ++S));
|
|
continue;
|
|
} else
|
|
Stack.push_back(std::make_pair(PredMBB, S+1));
|
|
|
|
MachineBasicBlock* MBB = *S;
|
|
Visited.insert(MBB);
|
|
|
|
if (MBB == BarrierMBB)
|
|
return true;
|
|
|
|
MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
|
|
MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
|
|
MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
|
|
while (MDTN) {
|
|
if (MDTN == DefMDTN)
|
|
return true;
|
|
else if (MDTN == BarrierMDTN)
|
|
break;
|
|
MDTN = MDTN->getIDom();
|
|
}
|
|
|
|
MBBEnd = LIs->getMBBEndIdx(MBB);
|
|
if (LR->end > MBBEnd)
|
|
Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
|
|
CurrMF = &MF;
|
|
TM = &MF.getTarget();
|
|
TRI = TM->getRegisterInfo();
|
|
TII = TM->getInstrInfo();
|
|
MFI = MF.getFrameInfo();
|
|
MRI = &MF.getRegInfo();
|
|
SIs = &getAnalysis<SlotIndexes>();
|
|
LIs = &getAnalysis<LiveIntervals>();
|
|
LSs = &getAnalysis<LiveStacks>();
|
|
VRM = &getAnalysis<VirtRegMap>();
|
|
|
|
bool MadeChange = false;
|
|
|
|
// Make sure blocks are numbered in order.
|
|
MF.RenumberBlocks();
|
|
|
|
MachineBasicBlock *Entry = MF.begin();
|
|
SmallPtrSet<MachineBasicBlock*,16> Visited;
|
|
|
|
SmallPtrSet<LiveInterval*, 8> Split;
|
|
|
|
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
|
|
DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
|
|
DFI != E; ++DFI) {
|
|
BarrierMBB = *DFI;
|
|
for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
|
|
E = BarrierMBB->end(); I != E; ++I) {
|
|
Barrier = &*I;
|
|
const TargetRegisterClass **BarrierRCs =
|
|
Barrier->getDesc().getRegClassBarriers();
|
|
if (!BarrierRCs)
|
|
continue;
|
|
BarrierIdx = LIs->getInstructionIndex(Barrier);
|
|
MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
|
|
}
|
|
}
|
|
|
|
MadeChange |= removeDeadSpills(Split);
|
|
|
|
return MadeChange;
|
|
}
|