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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
760 lines
25 KiB
C++
760 lines
25 KiB
C++
//===-- StackSlotColoring.cpp - Stack slot coloring pass. -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the stack slot coloring pass.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "stackcoloring"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include <vector>
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using namespace llvm;
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static cl::opt<bool>
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DisableSharing("no-stack-slot-sharing",
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cl::init(false), cl::Hidden,
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cl::desc("Suppress slot sharing during stack coloring"));
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static cl::opt<bool>
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ColorWithRegsOpt("color-ss-with-regs",
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cl::init(false), cl::Hidden,
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cl::desc("Color stack slots with free registers"));
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static cl::opt<int> DCELimit("ssc-dce-limit", cl::init(-1), cl::Hidden);
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STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring");
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STATISTIC(NumRegRepl, "Number of stack slot refs replaced with reg refs");
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STATISTIC(NumLoadElim, "Number of loads eliminated");
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STATISTIC(NumStoreElim, "Number of stores eliminated");
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STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
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namespace {
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class StackSlotColoring : public MachineFunctionPass {
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bool ColorWithRegs;
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LiveStacks* LS;
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VirtRegMap* VRM;
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MachineFrameInfo *MFI;
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const MachineLoopInfo *loopInfo;
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// SSIntervals - Spill slot intervals.
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std::vector<LiveInterval*> SSIntervals;
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// SSRefs - Keep a list of frame index references for each spill slot.
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SmallVector<SmallVector<MachineInstr*, 8>, 16> SSRefs;
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// OrigAlignments - Alignments of stack objects before coloring.
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SmallVector<unsigned, 16> OrigAlignments;
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// OrigSizes - Sizess of stack objects before coloring.
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SmallVector<unsigned, 16> OrigSizes;
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// AllColors - If index is set, it's a spill slot, i.e. color.
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// FIXME: This assumes PEI locate spill slot with smaller indices
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// closest to stack pointer / frame pointer. Therefore, smaller
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// index == better color.
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BitVector AllColors;
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// NextColor - Next "color" that's not yet used.
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int NextColor;
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// UsedColors - "Colors" that have been assigned.
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BitVector UsedColors;
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// Assignments - Color to intervals mapping.
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SmallVector<SmallVector<LiveInterval*,4>, 16> Assignments;
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public:
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static char ID; // Pass identification
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StackSlotColoring() :
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MachineFunctionPass(ID), ColorWithRegs(false), NextColor(-1) {}
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StackSlotColoring(bool RegColor) :
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MachineFunctionPass(ID), ColorWithRegs(RegColor), NextColor(-1) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveStacks>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char* getPassName() const {
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return "Stack Slot Coloring";
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}
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private:
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void InitializeSlots();
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bool CheckForSetJmpCall(const MachineFunction &MF) const;
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void ScanForSpillSlotRefs(MachineFunction &MF);
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bool OverlapWithAssignments(LiveInterval *li, int Color) const;
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int ColorSlot(LiveInterval *li);
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bool ColorSlots(MachineFunction &MF);
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bool ColorSlotsWithFreeRegs(SmallVector<int, 16> &SlotMapping,
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SmallVector<SmallVector<int, 4>, 16> &RevMap,
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BitVector &SlotIsReg);
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void RewriteInstruction(MachineInstr *MI, int OldFI, int NewFI,
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MachineFunction &MF);
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bool PropagateBackward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg);
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bool PropagateForward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg);
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void UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
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unsigned Reg, const TargetRegisterClass *RC,
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SmallSet<unsigned, 4> &Defs,
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MachineFunction &MF);
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bool AllMemRefsCanBeUnfolded(int SS);
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bool RemoveDeadStores(MachineBasicBlock* MBB);
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};
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} // end anonymous namespace
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char StackSlotColoring::ID = 0;
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INITIALIZE_PASS(StackSlotColoring, "stack-slot-coloring",
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"Stack Slot Coloring", false, false);
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FunctionPass *llvm::createStackSlotColoringPass(bool RegColor) {
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return new StackSlotColoring(RegColor);
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}
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namespace {
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// IntervalSorter - Comparison predicate that sort live intervals by
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// their weight.
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struct IntervalSorter {
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bool operator()(LiveInterval* LHS, LiveInterval* RHS) const {
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return LHS->weight > RHS->weight;
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}
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};
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}
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/// ScanForSpillSlotRefs - Scan all the machine instructions for spill slot
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/// references and update spill slot weights.
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void StackSlotColoring::ScanForSpillSlotRefs(MachineFunction &MF) {
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SSRefs.resize(MFI->getObjectIndexEnd());
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// FIXME: Need the equivalent of MachineRegisterInfo for frameindex operands.
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for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock *MBB = &*MBBI;
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unsigned loopDepth = loopInfo->getLoopDepth(MBB);
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for (MachineBasicBlock::iterator MII = MBB->begin(), EE = MBB->end();
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MII != EE; ++MII) {
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MachineInstr *MI = &*MII;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isFI())
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continue;
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int FI = MO.getIndex();
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if (FI < 0)
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continue;
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if (!LS->hasInterval(FI))
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continue;
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LiveInterval &li = LS->getInterval(FI);
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if (!MI->isDebugValue())
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li.weight += LiveIntervals::getSpillWeight(false, true, loopDepth);
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SSRefs[FI].push_back(MI);
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}
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}
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}
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}
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/// InitializeSlots - Process all spill stack slot liveintervals and add them
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/// to a sorted (by weight) list.
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void StackSlotColoring::InitializeSlots() {
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int LastFI = MFI->getObjectIndexEnd();
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OrigAlignments.resize(LastFI);
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OrigSizes.resize(LastFI);
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AllColors.resize(LastFI);
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UsedColors.resize(LastFI);
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Assignments.resize(LastFI);
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// Gather all spill slots into a list.
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DEBUG(dbgs() << "Spill slot intervals:\n");
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for (LiveStacks::iterator i = LS->begin(), e = LS->end(); i != e; ++i) {
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LiveInterval &li = i->second;
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DEBUG(li.dump());
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int FI = li.getStackSlotIndex();
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if (MFI->isDeadObjectIndex(FI))
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continue;
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SSIntervals.push_back(&li);
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OrigAlignments[FI] = MFI->getObjectAlignment(FI);
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OrigSizes[FI] = MFI->getObjectSize(FI);
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AllColors.set(FI);
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}
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DEBUG(dbgs() << '\n');
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// Sort them by weight.
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std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter());
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// Get first "color".
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NextColor = AllColors.find_first();
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}
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/// OverlapWithAssignments - Return true if LiveInterval overlaps with any
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/// LiveIntervals that have already been assigned to the specified color.
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bool
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StackSlotColoring::OverlapWithAssignments(LiveInterval *li, int Color) const {
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const SmallVector<LiveInterval*,4> &OtherLIs = Assignments[Color];
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for (unsigned i = 0, e = OtherLIs.size(); i != e; ++i) {
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LiveInterval *OtherLI = OtherLIs[i];
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if (OtherLI->overlaps(*li))
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return true;
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}
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return false;
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}
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/// ColorSlotsWithFreeRegs - If there are any free registers available, try
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/// replacing spill slots references with registers instead.
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bool
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StackSlotColoring::ColorSlotsWithFreeRegs(SmallVector<int, 16> &SlotMapping,
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SmallVector<SmallVector<int, 4>, 16> &RevMap,
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BitVector &SlotIsReg) {
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if (!(ColorWithRegs || ColorWithRegsOpt) || !VRM->HasUnusedRegisters())
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return false;
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bool Changed = false;
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DEBUG(dbgs() << "Assigning unused registers to spill slots:\n");
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for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
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LiveInterval *li = SSIntervals[i];
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int SS = li->getStackSlotIndex();
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if (!UsedColors[SS] || li->weight < 20)
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// If the weight is < 20, i.e. two references in a loop with depth 1,
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// don't bother with it.
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continue;
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// These slots allow to share the same registers.
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bool AllColored = true;
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SmallVector<unsigned, 4> ColoredRegs;
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for (unsigned j = 0, ee = RevMap[SS].size(); j != ee; ++j) {
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int RSS = RevMap[SS][j];
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const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS);
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// If it's not colored to another stack slot, try coloring it
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// to a "free" register.
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if (!RC) {
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AllColored = false;
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continue;
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}
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unsigned Reg = VRM->getFirstUnusedRegister(RC);
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if (!Reg) {
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AllColored = false;
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continue;
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}
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if (!AllMemRefsCanBeUnfolded(RSS)) {
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AllColored = false;
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continue;
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} else {
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DEBUG(dbgs() << "Assigning fi#" << RSS << " to "
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<< TRI->getName(Reg) << '\n');
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ColoredRegs.push_back(Reg);
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SlotMapping[RSS] = Reg;
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SlotIsReg.set(RSS);
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Changed = true;
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}
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}
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// Register and its sub-registers are no longer free.
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while (!ColoredRegs.empty()) {
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unsigned Reg = ColoredRegs.back();
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ColoredRegs.pop_back();
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VRM->setRegisterUsed(Reg);
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// If reg is a callee-saved register, it will have to be spilled in
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// the prologue.
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MRI->setPhysRegUsed(Reg);
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
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VRM->setRegisterUsed(*AS);
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MRI->setPhysRegUsed(*AS);
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}
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}
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// This spill slot is dead after the rewrites
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if (AllColored) {
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MFI->RemoveStackObject(SS);
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++NumEliminated;
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}
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}
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DEBUG(dbgs() << '\n');
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return Changed;
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}
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/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot.
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///
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int StackSlotColoring::ColorSlot(LiveInterval *li) {
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int Color = -1;
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bool Share = false;
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if (!DisableSharing) {
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// Check if it's possible to reuse any of the used colors.
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Color = UsedColors.find_first();
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while (Color != -1) {
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if (!OverlapWithAssignments(li, Color)) {
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Share = true;
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++NumEliminated;
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break;
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}
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Color = UsedColors.find_next(Color);
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}
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}
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// Assign it to the first available color (assumed to be the best) if it's
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// not possible to share a used color with other objects.
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if (!Share) {
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assert(NextColor != -1 && "No more spill slots?");
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Color = NextColor;
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UsedColors.set(Color);
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NextColor = AllColors.find_next(NextColor);
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}
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// Record the assignment.
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Assignments[Color].push_back(li);
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int FI = li->getStackSlotIndex();
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DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n");
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// Change size and alignment of the allocated slot. If there are multiple
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// objects sharing the same slot, then make sure the size and alignment
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// are large enough for all.
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unsigned Align = OrigAlignments[FI];
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if (!Share || Align > MFI->getObjectAlignment(Color))
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MFI->setObjectAlignment(Color, Align);
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int64_t Size = OrigSizes[FI];
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if (!Share || Size > MFI->getObjectSize(Color))
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MFI->setObjectSize(Color, Size);
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return Color;
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}
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/// Colorslots - Color all spill stack slots and rewrite all frameindex machine
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/// operands in the function.
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bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
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unsigned NumObjs = MFI->getObjectIndexEnd();
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SmallVector<int, 16> SlotMapping(NumObjs, -1);
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SmallVector<float, 16> SlotWeights(NumObjs, 0.0);
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SmallVector<SmallVector<int, 4>, 16> RevMap(NumObjs);
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BitVector SlotIsReg(NumObjs);
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BitVector UsedColors(NumObjs);
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DEBUG(dbgs() << "Color spill slot intervals:\n");
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bool Changed = false;
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for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
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LiveInterval *li = SSIntervals[i];
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int SS = li->getStackSlotIndex();
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int NewSS = ColorSlot(li);
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assert(NewSS >= 0 && "Stack coloring failed?");
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SlotMapping[SS] = NewSS;
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RevMap[NewSS].push_back(SS);
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SlotWeights[NewSS] += li->weight;
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UsedColors.set(NewSS);
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Changed |= (SS != NewSS);
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}
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DEBUG(dbgs() << "\nSpill slots after coloring:\n");
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for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
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LiveInterval *li = SSIntervals[i];
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int SS = li->getStackSlotIndex();
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li->weight = SlotWeights[SS];
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}
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// Sort them by new weight.
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std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter());
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#ifndef NDEBUG
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for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i)
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DEBUG(SSIntervals[i]->dump());
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DEBUG(dbgs() << '\n');
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#endif
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// Can we "color" a stack slot with a unused register?
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Changed |= ColorSlotsWithFreeRegs(SlotMapping, RevMap, SlotIsReg);
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if (!Changed)
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return false;
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// Rewrite all MO_FrameIndex operands.
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SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
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for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
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bool isReg = SlotIsReg[SS];
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int NewFI = SlotMapping[SS];
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if (NewFI == -1 || (NewFI == (int)SS && !isReg))
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continue;
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const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
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SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
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for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
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if (!isReg)
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RewriteInstruction(RefMIs[i], SS, NewFI, MF);
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else {
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// Rewrite to use a register instead.
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unsigned MBBId = RefMIs[i]->getParent()->getNumber();
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SmallSet<unsigned, 4> &Defs = NewDefs[MBBId];
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UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
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}
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}
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// Delete unused stack slots.
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while (NextColor != -1) {
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DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor << "\n");
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MFI->RemoveStackObject(NextColor);
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NextColor = AllColors.find_next(NextColor);
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}
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return true;
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}
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/// AllMemRefsCanBeUnfolded - Return true if all references of the specified
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/// spill slot index can be unfolded.
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bool StackSlotColoring::AllMemRefsCanBeUnfolded(int SS) {
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SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
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for (unsigned i = 0, e = RefMIs.size(); i != e; ++i) {
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MachineInstr *MI = RefMIs[i];
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if (TII->isLoadFromStackSlot(MI, SS) ||
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TII->isStoreToStackSlot(MI, SS))
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// Restore and spill will become copies.
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return true;
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if (!TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), false, false))
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return false;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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MachineOperand &MO = MI->getOperand(j);
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if (MO.isFI() && MO.getIndex() != SS)
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// If it uses another frameindex, we can, currently* unfold it.
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return false;
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}
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}
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return true;
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}
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/// RewriteInstruction - Rewrite specified instruction by replacing references
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/// to old frame index with new one.
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void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
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int NewFI, MachineFunction &MF) {
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// Update the operands.
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for (unsigned i = 0, ee = MI->getNumOperands(); i != ee; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isFI())
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continue;
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int FI = MO.getIndex();
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if (FI != OldFI)
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continue;
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MO.setIndex(NewFI);
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}
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// Update the memory references. This changes the MachineMemOperands
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// directly. They may be in use by multiple instructions, however all
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// instructions using OldFI are being rewritten to use NewFI.
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const Value *OldSV = PseudoSourceValue::getFixedStack(OldFI);
|
|
const Value *NewSV = PseudoSourceValue::getFixedStack(NewFI);
|
|
for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
|
|
E = MI->memoperands_end(); I != E; ++I)
|
|
if ((*I)->getValue() == OldSV)
|
|
(*I)->setValue(NewSV);
|
|
}
|
|
|
|
/// PropagateBackward - Traverse backward and look for the definition of
|
|
/// OldReg. If it can successfully update all of the references with NewReg,
|
|
/// do so and return true.
|
|
bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
|
|
MachineBasicBlock *MBB,
|
|
unsigned OldReg, unsigned NewReg) {
|
|
if (MII == MBB->begin())
|
|
return false;
|
|
|
|
SmallVector<MachineOperand*, 4> Uses;
|
|
SmallVector<MachineOperand*, 4> Refs;
|
|
while (--MII != MBB->begin()) {
|
|
bool FoundDef = false; // Not counting 2address def.
|
|
|
|
Uses.clear();
|
|
const TargetInstrDesc &TID = MII->getDesc();
|
|
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MII->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0)
|
|
continue;
|
|
if (Reg == OldReg) {
|
|
if (MO.isImplicit())
|
|
return false;
|
|
|
|
// Abort the use is actually a sub-register def. We don't have enough
|
|
// information to figure out if it is really legal.
|
|
if (MO.getSubReg() || MII->isSubregToReg())
|
|
return false;
|
|
|
|
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
|
|
if (RC && !RC->contains(NewReg))
|
|
return false;
|
|
|
|
if (MO.isUse()) {
|
|
Uses.push_back(&MO);
|
|
} else {
|
|
Refs.push_back(&MO);
|
|
if (!MII->isRegTiedToUseOperand(i))
|
|
FoundDef = true;
|
|
}
|
|
} else if (TRI->regsOverlap(Reg, NewReg)) {
|
|
return false;
|
|
} else if (TRI->regsOverlap(Reg, OldReg)) {
|
|
if (!MO.isUse() || !MO.isKill())
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (FoundDef) {
|
|
// Found non-two-address def. Stop here.
|
|
for (unsigned i = 0, e = Refs.size(); i != e; ++i)
|
|
Refs[i]->setReg(NewReg);
|
|
return true;
|
|
}
|
|
|
|
// Two-address uses must be updated as well.
|
|
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
|
|
Refs.push_back(Uses[i]);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// PropagateForward - Traverse forward and look for the kill of OldReg. If
|
|
/// it can successfully update all of the uses with NewReg, do so and
|
|
/// return true.
|
|
bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
|
|
MachineBasicBlock *MBB,
|
|
unsigned OldReg, unsigned NewReg) {
|
|
if (MII == MBB->end())
|
|
return false;
|
|
|
|
SmallVector<MachineOperand*, 4> Uses;
|
|
while (++MII != MBB->end()) {
|
|
bool FoundKill = false;
|
|
const TargetInstrDesc &TID = MII->getDesc();
|
|
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MII->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0)
|
|
continue;
|
|
if (Reg == OldReg) {
|
|
if (MO.isDef() || MO.isImplicit())
|
|
return false;
|
|
|
|
// Abort the use is actually a sub-register use. We don't have enough
|
|
// information to figure out if it is really legal.
|
|
if (MO.getSubReg())
|
|
return false;
|
|
|
|
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
|
|
if (RC && !RC->contains(NewReg))
|
|
return false;
|
|
if (MO.isKill())
|
|
FoundKill = true;
|
|
|
|
Uses.push_back(&MO);
|
|
} else if (TRI->regsOverlap(Reg, NewReg) ||
|
|
TRI->regsOverlap(Reg, OldReg))
|
|
return false;
|
|
}
|
|
if (FoundKill) {
|
|
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
|
|
Uses[i]->setReg(NewReg);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// UnfoldAndRewriteInstruction - Rewrite specified instruction by unfolding
|
|
/// folded memory references and replacing those references with register
|
|
/// references instead.
|
|
void
|
|
StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
|
|
unsigned Reg,
|
|
const TargetRegisterClass *RC,
|
|
SmallSet<unsigned, 4> &Defs,
|
|
MachineFunction &MF) {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
|
|
if (PropagateForward(MI, MBB, DstReg, Reg)) {
|
|
DEBUG(dbgs() << "Eliminated load: ");
|
|
DEBUG(MI->dump());
|
|
++NumLoadElim;
|
|
} else {
|
|
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
|
|
DstReg).addReg(Reg);
|
|
++NumRegRepl;
|
|
}
|
|
|
|
if (!Defs.count(Reg)) {
|
|
// If this is the first use of Reg in this MBB and it wasn't previously
|
|
// defined in MBB, add it to livein.
|
|
MBB->addLiveIn(Reg);
|
|
Defs.insert(Reg);
|
|
}
|
|
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
|
|
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
|
|
DEBUG(dbgs() << "Eliminated store: ");
|
|
DEBUG(MI->dump());
|
|
++NumStoreElim;
|
|
} else {
|
|
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY), Reg)
|
|
.addReg(SrcReg);
|
|
++NumRegRepl;
|
|
}
|
|
|
|
// Remember reg has been defined in MBB.
|
|
Defs.insert(Reg);
|
|
} else {
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs);
|
|
Success = Success; // Silence compiler warning.
|
|
assert(Success && "Failed to unfold!");
|
|
MachineInstr *NewMI = NewMIs[0];
|
|
MBB->insert(MI, NewMI);
|
|
++NumRegRepl;
|
|
|
|
if (NewMI->readsRegister(Reg)) {
|
|
if (!Defs.count(Reg))
|
|
// If this is the first use of Reg in this MBB and it wasn't previously
|
|
// defined in MBB, add it to livein.
|
|
MBB->addLiveIn(Reg);
|
|
Defs.insert(Reg);
|
|
}
|
|
}
|
|
MBB->erase(MI);
|
|
}
|
|
|
|
/// RemoveDeadStores - Scan through a basic block and look for loads followed
|
|
/// by stores. If they're both using the same stack slot, then the store is
|
|
/// definitely dead. This could obviously be much more aggressive (consider
|
|
/// pairs with instructions between them), but such extensions might have a
|
|
/// considerable compile time impact.
|
|
bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
|
|
// FIXME: This could be much more aggressive, but we need to investigate
|
|
// the compile time impact of doing so.
|
|
bool changed = false;
|
|
|
|
SmallVector<MachineInstr*, 4> toErase;
|
|
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
|
|
I != E; ++I) {
|
|
if (DCELimit != -1 && (int)NumDead >= DCELimit)
|
|
break;
|
|
|
|
MachineBasicBlock::iterator NextMI = llvm::next(I);
|
|
if (NextMI == MBB->end()) continue;
|
|
|
|
int FirstSS, SecondSS;
|
|
unsigned LoadReg = 0;
|
|
unsigned StoreReg = 0;
|
|
if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue;
|
|
if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
|
|
if (FirstSS != SecondSS || LoadReg != StoreReg || FirstSS == -1) continue;
|
|
|
|
++NumDead;
|
|
changed = true;
|
|
|
|
if (NextMI->findRegisterUseOperandIdx(LoadReg, true, 0) != -1) {
|
|
++NumDead;
|
|
toErase.push_back(I);
|
|
}
|
|
|
|
toErase.push_back(NextMI);
|
|
++I;
|
|
}
|
|
|
|
for (SmallVector<MachineInstr*, 4>::iterator I = toErase.begin(),
|
|
E = toErase.end(); I != E; ++I)
|
|
(*I)->eraseFromParent();
|
|
|
|
return changed;
|
|
}
|
|
|
|
|
|
bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG({
|
|
dbgs() << "********** Stack Slot Coloring **********\n"
|
|
<< "********** Function: "
|
|
<< MF.getFunction()->getName() << '\n';
|
|
});
|
|
|
|
MFI = MF.getFrameInfo();
|
|
MRI = &MF.getRegInfo();
|
|
TII = MF.getTarget().getInstrInfo();
|
|
TRI = MF.getTarget().getRegisterInfo();
|
|
LS = &getAnalysis<LiveStacks>();
|
|
VRM = &getAnalysis<VirtRegMap>();
|
|
loopInfo = &getAnalysis<MachineLoopInfo>();
|
|
|
|
bool Changed = false;
|
|
|
|
unsigned NumSlots = LS->getNumIntervals();
|
|
if (NumSlots < 2) {
|
|
if (NumSlots == 0 || !VRM->HasUnusedRegisters())
|
|
// Nothing to do!
|
|
return false;
|
|
}
|
|
|
|
// If there are calls to setjmp or sigsetjmp, don't perform stack slot
|
|
// coloring. The stack could be modified before the longjmp is executed,
|
|
// resulting in the wrong value being used afterwards. (See
|
|
// <rdar://problem/8007500>.)
|
|
if (MF.callsSetJmp())
|
|
return false;
|
|
|
|
// Gather spill slot references
|
|
ScanForSpillSlotRefs(MF);
|
|
InitializeSlots();
|
|
Changed = ColorSlots(MF);
|
|
|
|
NextColor = -1;
|
|
SSIntervals.clear();
|
|
for (unsigned i = 0, e = SSRefs.size(); i != e; ++i)
|
|
SSRefs[i].clear();
|
|
SSRefs.clear();
|
|
OrigAlignments.clear();
|
|
OrigSizes.clear();
|
|
AllColors.clear();
|
|
UsedColors.clear();
|
|
for (unsigned i = 0, e = Assignments.size(); i != e; ++i)
|
|
Assignments[i].clear();
|
|
Assignments.clear();
|
|
|
|
if (Changed) {
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
|
|
Changed |= RemoveDeadStores(I);
|
|
}
|
|
|
|
return Changed;
|
|
}
|