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e4b9c4f187
If we are emitting COPY instructions for the REG_SEQUENCE, make sure the kill flag goes on the last COPY. Otherwise we may be using a killed register. <rdar://problem/8287792> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110589 91177308-0d34-0410-b5e6-96231b3b80d8
1499 lines
56 KiB
C++
1499 lines
56 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A op= C
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//
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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STATISTIC(NumReMats, "Number of instructions re-materialized");
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STATISTIC(NumDeletes, "Number of dead instructions deleted");
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namespace {
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class TwoAddressInstructionPass : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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AliasAnalysis *AA;
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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// SrcRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies from physical
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// registers to virtual registers. e.g. v1024 = move r0.
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DenseMap<unsigned, unsigned> SrcRegMap;
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// DstRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies to physical
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// registers from virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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/// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
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/// during the initial walk of the machine function.
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SmallVector<MachineInstr*, 16> RegSequences;
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc);
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bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef);
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MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
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unsigned Dist);
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bool isProfitableToCommute(unsigned regB, unsigned regC,
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MachineInstr *MI, MachineBasicBlock *MBB,
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unsigned Dist);
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bool CommuteInstruction(MachineBasicBlock::iterator &mi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned RegC, unsigned Dist);
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bool isProfitableToConv3Addr(unsigned RegA);
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bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned Dist);
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typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
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bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
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SmallVector<NewKill, 4> &NewKills,
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MachineBasicBlock *MBB, unsigned Dist);
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bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi, unsigned Dist);
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bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned SrcIdx, unsigned DstIdx,
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unsigned Dist);
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
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/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
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/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
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/// sub-register references of the register defined by REG_SEQUENCE.
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bool EliminateRegSequences();
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Pass entry point.
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bool runOnMachineFunction(MachineFunction&);
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};
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}
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char TwoAddressInstructionPass::ID = 0;
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static RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(TII, AA, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = NULL;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SavedReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
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return false;
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// If any of the definitions are used by another instruction between the
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// position and the kill use, then it's not safe to sink it.
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//
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// FIXME: This can be sped up if there is an easy way to query whether an
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// instruction is before or after another instruction. Then we can use
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// MachineRegisterInfo def / use instead.
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MachineOperand *KillMO = NULL;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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unsigned NumVisited = 0;
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for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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// DBG_VALUE cannot be counted against the limit.
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if (OtherMI->isDebugValue())
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continue;
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if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
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return false;
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++NumVisited;
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (DefReg == MOReg)
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return false;
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if (MO.isKill()) {
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if (OtherMI == KillMI && MOReg == SavedReg)
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// Save the operand that kills the register. We want to unset the kill
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// marker if we can sink MI past it.
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KillMO = &MO;
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else if (UseRegs.count(MOReg))
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// One of the uses is killed before the destination.
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return false;
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}
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}
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}
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// Update kill and LV information.
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KillMO->setIsKill(false);
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KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
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KillMO->setIsKill(true);
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if (LV)
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LV->replaceKillInstruction(SavedReg, KillMI, MI);
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// Move instruction to its destination.
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MBB->remove(MI);
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MBB->insert(KillPos, MI);
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++Num3AddrSunk;
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return true;
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}
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/// isTwoAddrUse - Return true if the specified MI is using the specified
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/// register as a two-address operand.
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static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
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const TargetInstrDesc &TID = UseMI->getDesc();
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = UseMI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg &&
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(MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
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// Earlier use is a two-address one.
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return true;
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}
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return false;
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}
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/// isProfitableToReMat - Return true if the heuristics determines it is likely
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/// to be profitable to re-materialize the definition of Reg rather than copy
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/// the register.
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bool
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TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
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const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc) {
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bool OtherUse = false;
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for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = UseMO.getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
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if (DI != DistanceMap.end() && DI->second == Loc)
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continue; // Current use.
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OtherUse = true;
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// There is at least one other use in the MBB that will clobber the
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// register.
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if (isTwoAddrUse(UseMI, Reg))
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return true;
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}
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}
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// If other uses in MBB are not two-address uses, then don't remat.
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if (OtherUse)
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return false;
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// No other uses in the same block, remat if it's defined in the same
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// block so it does not unnecessarily extend the live range.
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return MBB == DefMI->getParent();
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}
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/// NoUseAfterLastDef - Return true if there are no intervening uses between the
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/// last instruction in the MBB that defines the specified register and the
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/// two-address instruction which is being processed. It also returns the last
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/// def location by reference
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bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
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MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef) {
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LastDef = 0;
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unsigned LastUse = Dist;
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
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E = MRI->reg_end(); I != E; ++I) {
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MachineOperand &MO = I.getOperand();
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MachineInstr *MI = MO.getParent();
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if (MI->getParent() != MBB || MI->isDebugValue())
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continue;
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
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if (DI == DistanceMap.end())
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continue;
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if (MO.isUse() && DI->second < LastUse)
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LastUse = DI->second;
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if (MO.isDef() && DI->second > LastDef)
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LastDef = DI->second;
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}
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return !(LastUse > LastDef && LastUse < Dist);
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}
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MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
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MachineBasicBlock *MBB,
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unsigned Dist) {
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unsigned LastUseDist = 0;
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MachineInstr *LastUse = 0;
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
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E = MRI->reg_end(); I != E; ++I) {
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MachineOperand &MO = I.getOperand();
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MachineInstr *MI = MO.getParent();
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if (MI->getParent() != MBB || MI->isDebugValue())
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continue;
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
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if (DI == DistanceMap.end())
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continue;
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if (DI->second >= Dist)
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continue;
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if (MO.isUse() && DI->second > LastUseDist) {
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LastUse = DI->first;
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LastUseDist = DI->second;
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}
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}
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return LastUse;
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}
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/// isCopyToReg - Return true if the specified MI is a copy instruction or
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/// a extract_subreg instruction. It also returns the source and destination
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/// registers and whether they are physical registers by reference.
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static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
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unsigned &SrcReg, unsigned &DstReg,
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bool &IsSrcPhys, bool &IsDstPhys) {
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SrcReg = 0;
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DstReg = 0;
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if (MI.isCopy()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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} else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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} else
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return false;
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IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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return true;
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}
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/// isKilled - Test if the given register value, which is used by the given
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/// instruction, is killed by the given instruction. This looks through
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/// coalescable copies to see if the original value is potentially not killed.
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///
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/// For example, in this code:
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///
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/// %reg1034 = copy %reg1024
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/// %reg1035 = copy %reg1025<kill>
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/// %reg1036 = add %reg1034<kill>, %reg1035<kill>
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///
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/// %reg1034 is not considered to be killed, since it is copied from a
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/// register which is not killed. Treating it as not killed lets the
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/// normal heuristics commute the (two-address) add, which lets
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/// coalescing eliminate the extra copy.
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///
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static bool isKilled(MachineInstr &MI, unsigned Reg,
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const MachineRegisterInfo *MRI,
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const TargetInstrInfo *TII) {
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MachineInstr *DefMI = &MI;
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for (;;) {
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if (!DefMI->killsRegister(Reg))
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return true;
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MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
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// If there are multiple defs, we can't do a simple analysis, so just
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// go with what the kill flag says.
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if (llvm::next(Begin) != MRI->def_end())
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return true;
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DefMI = &*Begin;
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bool IsSrcPhys, IsDstPhys;
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unsigned SrcReg, DstReg;
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// If the def is something other than a copy, then it isn't going to
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// be coalesced, so follow the kill flag.
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if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
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return true;
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Reg = SrcReg;
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}
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}
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/// isTwoAddrUse - Return true if the specified MI uses the specified register
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/// as a two-address use. If so, return the destination register by reference.
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static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
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const TargetInstrDesc &TID = MI.getDesc();
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unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands();
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for (unsigned i = 0; i != NumOps; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
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continue;
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unsigned ti;
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if (MI.isRegTiedToDefOperand(i, &ti)) {
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DstReg = MI.getOperand(ti).getReg();
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return true;
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}
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}
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return false;
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}
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/// findOnlyInterestingUse - Given a register, if has a single in-basic block
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/// use, return the use instruction if it's a copy or a two-address use.
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static
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MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
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MachineRegisterInfo *MRI,
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const TargetInstrInfo *TII,
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bool &IsCopy,
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unsigned &DstReg, bool &IsDstPhys) {
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if (!MRI->hasOneNonDBGUse(Reg))
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// None or more than one use.
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return 0;
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MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
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if (UseMI.getParent() != MBB)
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return 0;
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unsigned SrcReg;
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bool IsSrcPhys;
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if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
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IsCopy = true;
|
|
return &UseMI;
|
|
}
|
|
IsDstPhys = false;
|
|
if (isTwoAddrUse(UseMI, Reg, DstReg)) {
|
|
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
|
return &UseMI;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/// getMappedReg - Return the physical register the specified virtual register
|
|
/// might be mapped to.
|
|
static unsigned
|
|
getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
|
|
while (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
|
|
if (SI == RegMap.end())
|
|
return 0;
|
|
Reg = SI->second;
|
|
}
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
return Reg;
|
|
return 0;
|
|
}
|
|
|
|
/// regsAreCompatible - Return true if the two registers are equal or aliased.
|
|
///
|
|
static bool
|
|
regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
|
|
if (RegA == RegB)
|
|
return true;
|
|
if (!RegA || !RegB)
|
|
return false;
|
|
return TRI->regsOverlap(RegA, RegB);
|
|
}
|
|
|
|
|
|
/// isProfitableToReMat - Return true if it's potentially profitable to commute
|
|
/// the two-address instruction that's being processed.
|
|
bool
|
|
TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
|
|
MachineInstr *MI, MachineBasicBlock *MBB,
|
|
unsigned Dist) {
|
|
// Determine if it's profitable to commute this two address instruction. In
|
|
// general, we want no uses between this instruction and the definition of
|
|
// the two-address register.
|
|
// e.g.
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
// insert => %reg1030<def> = MOV8rr %reg1028
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
// In this case, it might not be possible to coalesce the second MOV8rr
|
|
// instruction if the first one is coalesced. So it would be profitable to
|
|
// commute it:
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
// insert => %reg1030<def> = MOV8rr %reg1029
|
|
// %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
|
|
|
|
if (!MI->killsRegister(regC))
|
|
return false;
|
|
|
|
// Ok, we have something like:
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
// let's see if it's worth commuting it.
|
|
|
|
// Look for situations like this:
|
|
// %reg1024<def> = MOV r1
|
|
// %reg1025<def> = MOV r0
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
// r0 = MOV %reg1026
|
|
// Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
|
|
unsigned FromRegB = getMappedReg(regB, SrcRegMap);
|
|
unsigned FromRegC = getMappedReg(regC, SrcRegMap);
|
|
unsigned ToRegB = getMappedReg(regB, DstRegMap);
|
|
unsigned ToRegC = getMappedReg(regC, DstRegMap);
|
|
if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
|
|
(regsAreCompatible(FromRegB, ToRegC, TRI) ||
|
|
regsAreCompatible(FromRegC, ToRegB, TRI)))
|
|
return true;
|
|
|
|
// If there is a use of regC between its last def (could be livein) and this
|
|
// instruction, then bail.
|
|
unsigned LastDefC = 0;
|
|
if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
|
|
return false;
|
|
|
|
// If there is a use of regB between its last def (could be livein) and this
|
|
// instruction, then go ahead and make this transformation.
|
|
unsigned LastDefB = 0;
|
|
if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
|
|
return true;
|
|
|
|
// Since there are no intervening uses for both registers, then commute
|
|
// if the def of regC is closer. Its live interval is shorter.
|
|
return LastDefB && LastDefC && LastDefC > LastDefB;
|
|
}
|
|
|
|
/// CommuteInstruction - Commute a two-address instruction and update the basic
|
|
/// block, distance map, and live variables if needed. Return true if it is
|
|
/// successful.
|
|
bool
|
|
TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
|
|
MachineFunction::iterator &mbbi,
|
|
unsigned RegB, unsigned RegC, unsigned Dist) {
|
|
MachineInstr *MI = mi;
|
|
DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
|
|
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
|
|
|
if (NewMI == 0) {
|
|
DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
|
|
return false;
|
|
}
|
|
|
|
DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
|
|
// If the instruction changed to commute it, update livevar.
|
|
if (NewMI != MI) {
|
|
if (LV)
|
|
// Update live variables
|
|
LV->replaceKillInstruction(RegC, MI, NewMI);
|
|
|
|
mbbi->insert(mi, NewMI); // Insert the new inst
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
mi = NewMI;
|
|
DistanceMap.insert(std::make_pair(NewMI, Dist));
|
|
}
|
|
|
|
// Update source register map.
|
|
unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
|
|
if (FromRegC) {
|
|
unsigned RegA = MI->getOperand(0).getReg();
|
|
SrcRegMap[RegA] = FromRegC;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isProfitableToConv3Addr - Return true if it is profitable to convert the
|
|
/// given 2-address instruction to a 3-address one.
|
|
bool
|
|
TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
|
|
// Look for situations like this:
|
|
// %reg1024<def> = MOV r1
|
|
// %reg1025<def> = MOV r0
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
// r2 = MOV %reg1026
|
|
// Turn ADD into a 3-address instruction to avoid a copy.
|
|
unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
|
|
unsigned ToRegA = getMappedReg(RegA, DstRegMap);
|
|
return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
|
|
}
|
|
|
|
/// ConvertInstTo3Addr - Convert the specified two-address instruction into a
|
|
/// three address one. Return true if this transformation was successful.
|
|
bool
|
|
TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
MachineFunction::iterator &mbbi,
|
|
unsigned RegB, unsigned Dist) {
|
|
MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
|
|
if (NewMI) {
|
|
DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
|
|
DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
|
|
bool Sunk = false;
|
|
|
|
if (NewMI->findRegisterUseOperand(RegB, false, TRI))
|
|
// FIXME: Temporary workaround. If the new instruction doesn't
|
|
// uses RegB, convertToThreeAddress must have created more
|
|
// then one instruction.
|
|
Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
if (!Sunk) {
|
|
DistanceMap.insert(std::make_pair(NewMI, Dist));
|
|
mi = NewMI;
|
|
nmi = llvm::next(mi);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// ProcessCopy - If the specified instruction is not yet processed, process it
|
|
/// if it's a copy. For a copy instruction, we find the physical registers the
|
|
/// source and destination registers might be mapped to. These are kept in
|
|
/// point-to maps used to determine future optimizations. e.g.
|
|
/// v1024 = mov r0
|
|
/// v1025 = mov r1
|
|
/// v1026 = add v1024, v1025
|
|
/// r1 = mov r1026
|
|
/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
|
|
/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
|
|
/// potentially joined with r1 on the output side. It's worthwhile to commute
|
|
/// 'add' to eliminate a copy.
|
|
void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
SmallPtrSet<MachineInstr*, 8> &Processed) {
|
|
if (Processed.count(MI))
|
|
return;
|
|
|
|
bool IsSrcPhys, IsDstPhys;
|
|
unsigned SrcReg, DstReg;
|
|
if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
|
|
return;
|
|
|
|
if (IsDstPhys && !IsSrcPhys)
|
|
DstRegMap.insert(std::make_pair(SrcReg, DstReg));
|
|
else if (!IsDstPhys && IsSrcPhys) {
|
|
bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
|
|
if (!isNew)
|
|
assert(SrcRegMap[DstReg] == SrcReg &&
|
|
"Can't map to two src physical registers!");
|
|
|
|
SmallVector<unsigned, 4> VirtRegPairs;
|
|
bool IsCopy = false;
|
|
unsigned NewReg = 0;
|
|
while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
|
|
IsCopy, NewReg, IsDstPhys)) {
|
|
if (IsCopy) {
|
|
if (!Processed.insert(UseMI))
|
|
break;
|
|
}
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
|
if (DI != DistanceMap.end())
|
|
// Earlier in the same MBB.Reached via a back edge.
|
|
break;
|
|
|
|
if (IsDstPhys) {
|
|
VirtRegPairs.push_back(NewReg);
|
|
break;
|
|
}
|
|
bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
|
|
if (!isNew)
|
|
assert(SrcRegMap[NewReg] == DstReg &&
|
|
"Can't map to two src physical registers!");
|
|
VirtRegPairs.push_back(NewReg);
|
|
DstReg = NewReg;
|
|
}
|
|
|
|
if (!VirtRegPairs.empty()) {
|
|
unsigned ToReg = VirtRegPairs.back();
|
|
VirtRegPairs.pop_back();
|
|
while (!VirtRegPairs.empty()) {
|
|
unsigned FromReg = VirtRegPairs.back();
|
|
VirtRegPairs.pop_back();
|
|
bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
|
|
if (!isNew)
|
|
assert(DstRegMap[FromReg] == ToReg &&
|
|
"Can't map to two dst physical registers!");
|
|
ToReg = FromReg;
|
|
}
|
|
}
|
|
}
|
|
|
|
Processed.insert(MI);
|
|
}
|
|
|
|
/// isSafeToDelete - If the specified instruction does not produce any side
|
|
/// effects and all of its defs are dead, then it's safe to delete.
|
|
static bool isSafeToDelete(MachineInstr *MI,
|
|
const TargetInstrInfo *TII,
|
|
SmallVector<unsigned, 4> &Kills) {
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
if (TID.mayStore() || TID.isCall())
|
|
return false;
|
|
if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
|
|
return false;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
if (MO.isDef() && !MO.isDead())
|
|
return false;
|
|
if (MO.isUse() && MO.isKill())
|
|
Kills.push_back(MO.getReg());
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// canUpdateDeletedKills - Check if all the registers listed in Kills are
|
|
/// killed by instructions in MBB preceding the current instruction at
|
|
/// position Dist. If so, return true and record information about the
|
|
/// preceding kills in NewKills.
|
|
bool TwoAddressInstructionPass::
|
|
canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
|
|
SmallVector<NewKill, 4> &NewKills,
|
|
MachineBasicBlock *MBB, unsigned Dist) {
|
|
while (!Kills.empty()) {
|
|
unsigned Kill = Kills.back();
|
|
Kills.pop_back();
|
|
if (TargetRegisterInfo::isPhysicalRegister(Kill))
|
|
return false;
|
|
|
|
MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
|
|
if (!LastKill)
|
|
return false;
|
|
|
|
bool isModRef = LastKill->definesRegister(Kill);
|
|
NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
|
|
LastKill));
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// DeleteUnusedInstr - If an instruction with a tied register operand can
|
|
/// be safely deleted, just delete it.
|
|
bool
|
|
TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
MachineFunction::iterator &mbbi,
|
|
unsigned Dist) {
|
|
// Check if the instruction has no side effects and if all its defs are dead.
|
|
SmallVector<unsigned, 4> Kills;
|
|
if (!isSafeToDelete(mi, TII, Kills))
|
|
return false;
|
|
|
|
// If this instruction kills some virtual registers, we need to
|
|
// update the kill information. If it's not possible to do so,
|
|
// then bail out.
|
|
SmallVector<NewKill, 4> NewKills;
|
|
if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
|
|
return false;
|
|
|
|
if (LV) {
|
|
while (!NewKills.empty()) {
|
|
MachineInstr *NewKill = NewKills.back().second;
|
|
unsigned Kill = NewKills.back().first.first;
|
|
bool isDead = NewKills.back().first.second;
|
|
NewKills.pop_back();
|
|
if (LV->removeVirtualRegisterKilled(Kill, mi)) {
|
|
if (isDead)
|
|
LV->addVirtualRegisterDead(Kill, NewKill);
|
|
else
|
|
LV->addVirtualRegisterKilled(Kill, NewKill);
|
|
}
|
|
}
|
|
}
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
mi = nmi;
|
|
return true;
|
|
}
|
|
|
|
/// TryInstructionTransform - For the case where an instruction has a single
|
|
/// pair of tied register operands, attempt some transformations that may
|
|
/// either eliminate the tied operands or improve the opportunities for
|
|
/// coalescing away the register copy. Returns true if the tied operands
|
|
/// are eliminated altogether.
|
|
bool TwoAddressInstructionPass::
|
|
TryInstructionTransform(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
MachineFunction::iterator &mbbi,
|
|
unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
|
|
const TargetInstrDesc &TID = mi->getDesc();
|
|
unsigned regA = mi->getOperand(DstIdx).getReg();
|
|
unsigned regB = mi->getOperand(SrcIdx).getReg();
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(regB) &&
|
|
"cannot make instruction into two-address form");
|
|
|
|
// If regA is dead and the instruction can be deleted, just delete
|
|
// it so it doesn't clobber regB.
|
|
bool regBKilled = isKilled(*mi, regB, MRI, TII);
|
|
if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
|
|
DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
|
|
++NumDeletes;
|
|
return true; // Done with this instruction.
|
|
}
|
|
|
|
// Check if it is profitable to commute the operands.
|
|
unsigned SrcOp1, SrcOp2;
|
|
unsigned regC = 0;
|
|
unsigned regCIdx = ~0U;
|
|
bool TryCommute = false;
|
|
bool AggressiveCommute = false;
|
|
if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
|
|
TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
|
|
if (SrcIdx == SrcOp1)
|
|
regCIdx = SrcOp2;
|
|
else if (SrcIdx == SrcOp2)
|
|
regCIdx = SrcOp1;
|
|
|
|
if (regCIdx != ~0U) {
|
|
regC = mi->getOperand(regCIdx).getReg();
|
|
if (!regBKilled && isKilled(*mi, regC, MRI, TII))
|
|
// If C dies but B does not, swap the B and C operands.
|
|
// This makes the live ranges of A and C joinable.
|
|
TryCommute = true;
|
|
else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
|
|
TryCommute = true;
|
|
AggressiveCommute = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// If it's profitable to commute, try to do so.
|
|
if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
|
|
++NumCommuted;
|
|
if (AggressiveCommute)
|
|
++NumAggrCommuted;
|
|
return false;
|
|
}
|
|
|
|
if (TID.isConvertibleTo3Addr()) {
|
|
// This instruction is potentially convertible to a true
|
|
// three-address instruction. Check if it is profitable.
|
|
if (!regBKilled || isProfitableToConv3Addr(regA)) {
|
|
// Try to convert it.
|
|
if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
|
|
++NumConvertedTo3Addr;
|
|
return true; // Done with this instruction.
|
|
}
|
|
}
|
|
}
|
|
|
|
// If this is an instruction with a load folded into it, try unfolding
|
|
// the load, e.g. avoid this:
|
|
// movq %rdx, %rcx
|
|
// addq (%rax), %rcx
|
|
// in favor of this:
|
|
// movq (%rax), %rcx
|
|
// addq %rdx, %rcx
|
|
// because it's preferable to schedule a load than a register copy.
|
|
if (TID.mayLoad() && !regBKilled) {
|
|
// Determine if a load can be unfolded.
|
|
unsigned LoadRegIndex;
|
|
unsigned NewOpc =
|
|
TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
|
|
/*UnfoldLoad=*/true,
|
|
/*UnfoldStore=*/false,
|
|
&LoadRegIndex);
|
|
if (NewOpc != 0) {
|
|
const TargetInstrDesc &UnfoldTID = TII->get(NewOpc);
|
|
if (UnfoldTID.getNumDefs() == 1) {
|
|
MachineFunction &MF = *mbbi->getParent();
|
|
|
|
// Unfold the load.
|
|
DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
|
|
const TargetRegisterClass *RC =
|
|
UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
|
|
unsigned Reg = MRI->createVirtualRegister(RC);
|
|
SmallVector<MachineInstr *, 2> NewMIs;
|
|
if (!TII->unfoldMemoryOperand(MF, mi, Reg,
|
|
/*UnfoldLoad=*/true,/*UnfoldStore=*/false,
|
|
NewMIs)) {
|
|
DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
|
|
return false;
|
|
}
|
|
assert(NewMIs.size() == 2 &&
|
|
"Unfolded a load into multiple instructions!");
|
|
// The load was previously folded, so this is the only use.
|
|
NewMIs[1]->addRegisterKilled(Reg, TRI);
|
|
|
|
// Tentatively insert the instructions into the block so that they
|
|
// look "normal" to the transformation logic.
|
|
mbbi->insert(mi, NewMIs[0]);
|
|
mbbi->insert(mi, NewMIs[1]);
|
|
|
|
DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
|
|
<< "2addr: NEW INST: " << *NewMIs[1]);
|
|
|
|
// Transform the instruction, now that it no longer has a load.
|
|
unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
|
|
unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
|
|
MachineBasicBlock::iterator NewMI = NewMIs[1];
|
|
bool TransformSuccess =
|
|
TryInstructionTransform(NewMI, mi, mbbi,
|
|
NewSrcIdx, NewDstIdx, Dist);
|
|
if (TransformSuccess ||
|
|
NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
|
|
// Success, or at least we made an improvement. Keep the unfolded
|
|
// instructions and discard the original.
|
|
if (LV) {
|
|
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = mi->getOperand(i);
|
|
if (MO.isReg() && MO.getReg() != 0 &&
|
|
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
if (MO.isUse()) {
|
|
if (MO.isKill()) {
|
|
if (NewMIs[0]->killsRegister(MO.getReg()))
|
|
LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
|
|
else {
|
|
assert(NewMIs[1]->killsRegister(MO.getReg()) &&
|
|
"Kill missing after load unfold!");
|
|
LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
|
|
}
|
|
}
|
|
} else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
|
|
if (NewMIs[1]->registerDefIsDead(MO.getReg()))
|
|
LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
|
|
else {
|
|
assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
|
|
"Dead flag missing after load unfold!");
|
|
LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
|
|
}
|
|
mi->eraseFromParent();
|
|
mi = NewMIs[1];
|
|
if (TransformSuccess)
|
|
return true;
|
|
} else {
|
|
// Transforming didn't eliminate the tie and didn't lead to an
|
|
// improvement. Clean up the unfolded instructions and keep the
|
|
// original.
|
|
DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
|
|
NewMIs[0]->eraseFromParent();
|
|
NewMIs[1]->eraseFromParent();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// runOnMachineFunction - Reduce two-address instructions to two operands.
|
|
///
|
|
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "Machine Function\n");
|
|
const TargetMachine &TM = MF.getTarget();
|
|
MRI = &MF.getRegInfo();
|
|
TII = TM.getInstrInfo();
|
|
TRI = TM.getRegisterInfo();
|
|
LV = getAnalysisIfAvailable<LiveVariables>();
|
|
AA = &getAnalysis<AliasAnalysis>();
|
|
|
|
bool MadeChange = false;
|
|
|
|
DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
|
|
DEBUG(dbgs() << "********** Function: "
|
|
<< MF.getFunction()->getName() << '\n');
|
|
|
|
// ReMatRegs - Keep track of the registers whose def's are remat'ed.
|
|
BitVector ReMatRegs;
|
|
ReMatRegs.resize(MRI->getLastVirtReg()+1);
|
|
|
|
typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
|
|
TiedOperandMap;
|
|
TiedOperandMap TiedOperands(4);
|
|
|
|
SmallPtrSet<MachineInstr*, 8> Processed;
|
|
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
|
|
mbbi != mbbe; ++mbbi) {
|
|
unsigned Dist = 0;
|
|
DistanceMap.clear();
|
|
SrcRegMap.clear();
|
|
DstRegMap.clear();
|
|
Processed.clear();
|
|
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
|
|
mi != me; ) {
|
|
MachineBasicBlock::iterator nmi = llvm::next(mi);
|
|
if (mi->isDebugValue()) {
|
|
mi = nmi;
|
|
continue;
|
|
}
|
|
|
|
// Remember REG_SEQUENCE instructions, we'll deal with them later.
|
|
if (mi->isRegSequence())
|
|
RegSequences.push_back(&*mi);
|
|
|
|
const TargetInstrDesc &TID = mi->getDesc();
|
|
bool FirstTied = true;
|
|
|
|
DistanceMap.insert(std::make_pair(mi, ++Dist));
|
|
|
|
ProcessCopy(&*mi, &*mbbi, Processed);
|
|
|
|
// First scan through all the tied register uses in this instruction
|
|
// and record a list of pairs of tied operands for each register.
|
|
unsigned NumOps = mi->isInlineAsm()
|
|
? mi->getNumOperands() : TID.getNumOperands();
|
|
for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
|
|
unsigned DstIdx = 0;
|
|
if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
|
|
continue;
|
|
|
|
if (FirstTied) {
|
|
FirstTied = false;
|
|
++NumTwoAddressInstrs;
|
|
DEBUG(dbgs() << '\t' << *mi);
|
|
}
|
|
|
|
assert(mi->getOperand(SrcIdx).isReg() &&
|
|
mi->getOperand(SrcIdx).getReg() &&
|
|
mi->getOperand(SrcIdx).isUse() &&
|
|
"two address instruction invalid");
|
|
|
|
unsigned regB = mi->getOperand(SrcIdx).getReg();
|
|
TiedOperandMap::iterator OI = TiedOperands.find(regB);
|
|
if (OI == TiedOperands.end()) {
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
|
|
OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
|
|
}
|
|
OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
|
|
}
|
|
|
|
// Now iterate over the information collected above.
|
|
for (TiedOperandMap::iterator OI = TiedOperands.begin(),
|
|
OE = TiedOperands.end(); OI != OE; ++OI) {
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
|
|
|
|
// If the instruction has a single pair of tied operands, try some
|
|
// transformations that may either eliminate the tied operands or
|
|
// improve the opportunities for coalescing away the register copy.
|
|
if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
|
|
unsigned SrcIdx = TiedPairs[0].first;
|
|
unsigned DstIdx = TiedPairs[0].second;
|
|
|
|
// If the registers are already equal, nothing needs to be done.
|
|
if (mi->getOperand(SrcIdx).getReg() ==
|
|
mi->getOperand(DstIdx).getReg())
|
|
break; // Done with this instruction.
|
|
|
|
if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
|
|
break; // The tied operands have been eliminated.
|
|
}
|
|
|
|
bool RemovedKillFlag = false;
|
|
bool AllUsesCopied = true;
|
|
unsigned LastCopiedReg = 0;
|
|
unsigned regB = OI->first;
|
|
for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
|
|
unsigned SrcIdx = TiedPairs[tpi].first;
|
|
unsigned DstIdx = TiedPairs[tpi].second;
|
|
unsigned regA = mi->getOperand(DstIdx).getReg();
|
|
// Grab regB from the instruction because it may have changed if the
|
|
// instruction was commuted.
|
|
regB = mi->getOperand(SrcIdx).getReg();
|
|
|
|
if (regA == regB) {
|
|
// The register is tied to multiple destinations (or else we would
|
|
// not have continued this far), but this use of the register
|
|
// already matches the tied destination. Leave it.
|
|
AllUsesCopied = false;
|
|
continue;
|
|
}
|
|
LastCopiedReg = regA;
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(regB) &&
|
|
"cannot make instruction into two-address form");
|
|
|
|
#ifndef NDEBUG
|
|
// First, verify that we don't have a use of "a" in the instruction
|
|
// (a = b + a for example) because our transformation will not
|
|
// work. This should never occur because we are in SSA form.
|
|
for (unsigned i = 0; i != mi->getNumOperands(); ++i)
|
|
assert(i == DstIdx ||
|
|
!mi->getOperand(i).isReg() ||
|
|
mi->getOperand(i).getReg() != regA);
|
|
#endif
|
|
|
|
// Emit a copy or rematerialize the definition.
|
|
const TargetRegisterClass *rc = MRI->getRegClass(regB);
|
|
MachineInstr *DefMI = MRI->getVRegDef(regB);
|
|
// If it's safe and profitable, remat the definition instead of
|
|
// copying it.
|
|
if (DefMI &&
|
|
DefMI->getDesc().isAsCheapAsAMove() &&
|
|
DefMI->isSafeToReMat(TII, AA, regB) &&
|
|
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
|
|
DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
|
|
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
|
|
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
|
|
ReMatRegs.set(regB);
|
|
++NumReMats;
|
|
} else {
|
|
BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
|
|
regA).addReg(regB);
|
|
}
|
|
|
|
MachineBasicBlock::iterator prevMI = prior(mi);
|
|
// Update DistanceMap.
|
|
DistanceMap.insert(std::make_pair(prevMI, Dist));
|
|
DistanceMap[mi] = ++Dist;
|
|
|
|
DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
|
|
|
|
MachineOperand &MO = mi->getOperand(SrcIdx);
|
|
assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
|
|
"inconsistent operand info for 2-reg pass");
|
|
if (MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
RemovedKillFlag = true;
|
|
}
|
|
MO.setReg(regA);
|
|
}
|
|
|
|
if (AllUsesCopied) {
|
|
// Replace other (un-tied) uses of regB with LastCopiedReg.
|
|
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = mi->getOperand(i);
|
|
if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
|
|
if (MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
RemovedKillFlag = true;
|
|
}
|
|
MO.setReg(LastCopiedReg);
|
|
}
|
|
}
|
|
|
|
// Update live variables for regB.
|
|
if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
|
|
LV->addVirtualRegisterKilled(regB, prior(mi));
|
|
|
|
} else if (RemovedKillFlag) {
|
|
// Some tied uses of regB matched their destination registers, so
|
|
// regB is still used in this instruction, but a kill flag was
|
|
// removed from a different tied use of regB, so now we need to add
|
|
// a kill flag to one of the remaining uses of regB.
|
|
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = mi->getOperand(i);
|
|
if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
|
|
MO.setIsKill(true);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Schedule the source copy / remat inserted to form two-address
|
|
// instruction. FIXME: Does it matter the distance map may not be
|
|
// accurate after it's scheduled?
|
|
TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
|
|
|
|
MadeChange = true;
|
|
|
|
DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
|
|
}
|
|
|
|
// Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
|
|
if (mi->isInsertSubreg()) {
|
|
// From %reg = INSERT_SUBREG %reg, %subreg, subidx
|
|
// To %reg:subidx = COPY %subreg
|
|
unsigned SubIdx = mi->getOperand(3).getImm();
|
|
mi->RemoveOperand(3);
|
|
assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
|
|
mi->getOperand(0).setSubReg(SubIdx);
|
|
mi->RemoveOperand(1);
|
|
mi->setDesc(TII->get(TargetOpcode::COPY));
|
|
DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
|
|
}
|
|
|
|
// Clear TiedOperands here instead of at the top of the loop
|
|
// since most instructions do not have tied operands.
|
|
TiedOperands.clear();
|
|
mi = nmi;
|
|
}
|
|
}
|
|
|
|
// Some remat'ed instructions are dead.
|
|
int VReg = ReMatRegs.find_first();
|
|
while (VReg != -1) {
|
|
if (MRI->use_nodbg_empty(VReg)) {
|
|
MachineInstr *DefMI = MRI->getVRegDef(VReg);
|
|
DefMI->eraseFromParent();
|
|
}
|
|
VReg = ReMatRegs.find_next(VReg);
|
|
}
|
|
|
|
// Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
|
|
// SSA form. It's now safe to de-SSA.
|
|
MadeChange |= EliminateRegSequences();
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
static void UpdateRegSequenceSrcs(unsigned SrcReg,
|
|
unsigned DstReg, unsigned SubIdx,
|
|
MachineRegisterInfo *MRI,
|
|
const TargetRegisterInfo &TRI) {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
|
|
RE = MRI->reg_end(); RI != RE; ) {
|
|
MachineOperand &MO = RI.getOperand();
|
|
++RI;
|
|
MO.substVirtReg(DstReg, SubIdx, TRI);
|
|
}
|
|
}
|
|
|
|
/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
|
|
/// EXTRACT_SUBREG from the same register and to the same virtual register
|
|
/// with different sub-register indices, attempt to combine the
|
|
/// EXTRACT_SUBREGs and pre-coalesce them. e.g.
|
|
/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
|
|
/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
|
|
/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
|
|
/// Since D subregs 5, 6 can combine to a Q register, we can coalesce
|
|
/// reg1026 to reg1029.
|
|
void
|
|
TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
|
|
unsigned DstReg) {
|
|
SmallSet<unsigned, 4> Seen;
|
|
for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
|
|
unsigned SrcReg = Srcs[i];
|
|
if (!Seen.insert(SrcReg))
|
|
continue;
|
|
|
|
// Check that the instructions are all in the same basic block.
|
|
MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
|
|
MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
|
|
if (SrcDefMI->getParent() != DstDefMI->getParent())
|
|
continue;
|
|
|
|
// If there are no other uses than copies which feed into
|
|
// the reg_sequence, then we might be able to coalesce them.
|
|
bool CanCoalesce = true;
|
|
SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
UI = MRI->use_nodbg_begin(SrcReg),
|
|
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
|
|
MachineInstr *UseMI = &*UI;
|
|
if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
|
|
CanCoalesce = false;
|
|
break;
|
|
}
|
|
SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
|
|
DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
|
|
}
|
|
|
|
if (!CanCoalesce || SrcSubIndices.size() < 2)
|
|
continue;
|
|
|
|
// Check that the source subregisters can be combined.
|
|
std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
|
|
unsigned NewSrcSubIdx = 0;
|
|
if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
|
|
NewSrcSubIdx))
|
|
continue;
|
|
|
|
// Check that the destination subregisters can also be combined.
|
|
std::sort(DstSubIndices.begin(), DstSubIndices.end());
|
|
unsigned NewDstSubIdx = 0;
|
|
if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
|
|
NewDstSubIdx))
|
|
continue;
|
|
|
|
// If neither source nor destination can be combined to the full register,
|
|
// just give up. This could be improved if it ever matters.
|
|
if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
|
|
continue;
|
|
|
|
// Now that we know that all the uses are extract_subregs and that those
|
|
// subregs can somehow be combined, scan all the extract_subregs again to
|
|
// make sure the subregs are in the right order and can be composed.
|
|
MachineInstr *SomeMI = 0;
|
|
CanCoalesce = true;
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
UI = MRI->use_nodbg_begin(SrcReg),
|
|
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
|
|
MachineInstr *UseMI = &*UI;
|
|
assert(UseMI->isCopy());
|
|
unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
|
|
unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
|
|
assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
|
|
if ((NewDstSubIdx == 0 &&
|
|
TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
|
|
(NewSrcSubIdx == 0 &&
|
|
TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
|
|
CanCoalesce = false;
|
|
break;
|
|
}
|
|
// Keep track of one of the uses.
|
|
SomeMI = UseMI;
|
|
}
|
|
if (!CanCoalesce)
|
|
continue;
|
|
|
|
// Insert a copy to replace the original.
|
|
MachineBasicBlock::iterator InsertLoc = SomeMI;
|
|
MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
|
|
SomeMI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY))
|
|
.addReg(DstReg, RegState::Define, NewDstSubIdx)
|
|
.addReg(SrcReg, 0, NewSrcSubIdx);
|
|
|
|
// Remove all the old extract instructions.
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
UI = MRI->use_nodbg_begin(SrcReg),
|
|
UE = MRI->use_nodbg_end(); UI != UE; ) {
|
|
MachineInstr *UseMI = &*UI;
|
|
++UI;
|
|
if (UseMI == CopyMI)
|
|
continue;
|
|
assert(UseMI->isCopy());
|
|
// Move any kills to the new copy or extract instruction.
|
|
if (UseMI->getOperand(1).isKill()) {
|
|
CopyMI->getOperand(1).setIsKill();
|
|
if (LV)
|
|
// Update live variables
|
|
LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
|
|
}
|
|
UseMI->eraseFromParent();
|
|
}
|
|
}
|
|
}
|
|
|
|
static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
|
|
MachineRegisterInfo *MRI) {
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
|
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
|
MachineInstr *UseMI = &*UI;
|
|
if (UseMI != RegSeq && UseMI->isRegSequence())
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
|
|
/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
|
|
/// sub-register references of the register defined by REG_SEQUENCE. e.g.
|
|
///
|
|
/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
|
|
/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
|
|
/// =>
|
|
/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
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bool TwoAddressInstructionPass::EliminateRegSequences() {
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if (RegSequences.empty())
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return false;
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for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
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MachineInstr *MI = RegSequences[i];
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unsigned DstReg = MI->getOperand(0).getReg();
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if (MI->getOperand(0).getSubReg() ||
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TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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!(MI->getNumOperands() & 1)) {
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DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
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llvm_unreachable(0);
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}
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|
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bool IsImpDef = true;
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SmallVector<unsigned, 4> RealSrcs;
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SmallSet<unsigned, 4> Seen;
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for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
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unsigned SrcReg = MI->getOperand(i).getReg();
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if (MI->getOperand(i).getSubReg() ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
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llvm_unreachable(0);
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}
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|
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MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
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|
if (DefMI->isImplicitDef()) {
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|
DefMI->eraseFromParent();
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continue;
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}
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|
IsImpDef = false;
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|
|
|
// Remember COPY sources. These might be candidate for coalescing.
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if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
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RealSrcs.push_back(DefMI->getOperand(1).getReg());
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|
|
|
bool isKill = MI->getOperand(i).isKill();
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|
if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
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!isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI)) {
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|
// REG_SEQUENCE cannot have duplicated operands, add a copy.
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|
// Also add an copy if the source is live-in the block. We don't want
|
|
// to end up with a partial-redef of a livein, e.g.
|
|
// BB0:
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|
// reg1051:10<def> =
|
|
// ...
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|
// BB1:
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|
// ... = reg1051:10
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|
// BB2:
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|
// reg1051:9<def> =
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|
// LiveIntervalAnalysis won't like it.
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|
//
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|
// If the REG_SEQUENCE doesn't kill its source, keeping live variables
|
|
// correctly up to date becomes very difficult. Insert a copy.
|
|
|
|
// Defer any kill flag to the last operand using SrcReg. Otherwise, we
|
|
// might insert a COPY that uses SrcReg after is was killed.
|
|
if (isKill)
|
|
for (unsigned j = i + 2; j < e; j += 2)
|
|
if (MI->getOperand(j).getReg() == SrcReg) {
|
|
MI->getOperand(j).setIsKill();
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|
isKill = false;
|
|
break;
|
|
}
|
|
|
|
MachineBasicBlock::iterator InsertLoc = MI;
|
|
MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
|
|
MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
|
|
.addReg(DstReg, RegState::Define, MI->getOperand(i+1).getImm())
|
|
.addReg(SrcReg, getKillRegState(isKill));
|
|
MI->getOperand(i).setReg(0);
|
|
if (LV && isKill)
|
|
LV->replaceKillInstruction(SrcReg, MI, CopyMI);
|
|
DEBUG(dbgs() << "Inserted: " << *CopyMI);
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
|
|
unsigned SrcReg = MI->getOperand(i).getReg();
|
|
if (!SrcReg) continue;
|
|
unsigned SubIdx = MI->getOperand(i+1).getImm();
|
|
UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
|
|
}
|
|
|
|
if (IsImpDef) {
|
|
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
|
|
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
|
|
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
|
|
MI->RemoveOperand(j);
|
|
} else {
|
|
DEBUG(dbgs() << "Eliminated: " << *MI);
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// Try coalescing some EXTRACT_SUBREG instructions. This can create
|
|
// INSERT_SUBREG instructions that must have <undef> flags added by
|
|
// LiveIntervalAnalysis, so only run it when LiveVariables is available.
|
|
if (LV)
|
|
CoalesceExtSubRegs(RealSrcs, DstReg);
|
|
}
|
|
|
|
RegSequences.clear();
|
|
return true;
|
|
}
|