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ac1a45e511
Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.2 KiB
LLVM
33 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -s -sd | FileCheck --check-prefix=ELF %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF
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; The SHT_NOTE section contains the output from the .hsa_code_object_*
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; directives.
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; ELF: SHT_NOTE
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; ELF: 0000: 04000000 08000000 01000000 414D4400
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; ELF: 0010: 01000000 00000000 04000000 1B000000
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; ELF: 0020: 03000000 414D4400 04000700 07000000
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; ELF: 0030: 00000000 00000000 414D4400 414D4447
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; ELF: 0040: 50550000
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; HSA: .hsa_code_object_version 1,0
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; HSA: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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; HSA: {{^}}simple:
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; HSA: .section .hsa.version
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; HSA-NEXT: .ascii "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
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; Test that the amd_kernel_code_t object is emitted
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; HSA: .asciz
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; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0
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; Make sure we are setting the ATC bit:
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; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
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; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
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define void @simple(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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